core: fix memory address comparison

Addresses are unsigned values. Subtracting address values results
in an unsigned value. Since qsort comparison function expects a signed
integer return value, the

core: fix memory address comparison

Addresses are unsigned values. Subtracting address values results
in an unsigned value. Since qsort comparison function expects a signed
integer return value, the unsigned address subtraction value gets
signed and can produce a wrong result. This change overcomes the issue
by producing a +1/0/-1 signed value based on the address unsigned
values comparison.

Introduce CMP_TRILEAN() in util.h to implement the operation.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: default enable program flow prediction on ARMv7 cores

Introduce CFG_ENABLE_SCTLR_Z to enable SCTLR[Z] from the generic boot.
SCTLR[Z] enables program flow prediction support from the core.

Ea

core: default enable program flow prediction on ARMv7 cores

Introduce CFG_ENABLE_SCTLR_Z to enable SCTLR[Z] from the generic boot.
SCTLR[Z] enables program flow prediction support from the core.

Early branch prediction may be unsafe against uncontrolled memory
prefetches that could hit some hard memory access control firewalls.
It is usually safer to enable after the mmu is enabled.

CFG_ENABLE_SCTLR_Z allows to use vanilla op-tee on development board
to exercises benchmark and performance tests over the op-tee system.

This feature is no expected on ARMv8 architectures and some recent
ARMv7 architectures since program flow prediction enable is tight to
mmu enable.

Suggested-by: Jangseop Shin <jsshin@sor.snu.ac.kr>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: clarify SCTLR initialization in 32bit mode.

Synchronize SCTLR init for primary cold boot and secondary cpu on
through the use of the macro 'set_sctlr' in generic_entry_a32.S.

Update STCLR ini

core: clarify SCTLR initialization in 32bit mode.

Synchronize SCTLR init for primary cold boot and secondary cpu on
through the use of the macro 'set_sctlr' in generic_entry_a32.S.

Update STCLR init to enforce TE=0 (exceptions in ARM mode) and M=0
(mmu off).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: default enable CFG_ENABLE_SCTLR_RR for some ARMv7 cores

Some platforms could benefit from CFG_ENABLE_SCTLR_RR according to
their current implementation.

Updated platforms are stm-(cannes2|b22

core: default enable CFG_ENABLE_SCTLR_RR for some ARMv7 cores

Some platforms could benefit from CFG_ENABLE_SCTLR_RR according to
their current implementation.

Updated platforms are stm-(cannes2|b2260), several mx6-*sabre*
mx6-(qsabrelite|qsabresd|dlsabresd) (CFG_MX6Q/_MX6D/_MX6DL/_MX6S)
and zynq-zc702.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: introduce CFG_ENABLE_SCTLR_RR for ARMv7 cores

CFG_ENABLE_SCTLR_RR to enable SCTLR[RR] from the generic boot.
SCTLR[RR] enables the round robin replacement strategy for the
several caches (icac

core: introduce CFG_ENABLE_SCTLR_RR for ARMv7 cores

CFG_ENABLE_SCTLR_RR to enable SCTLR[RR] from the generic boot.
SCTLR[RR] enables the round robin replacement strategy for the
several caches (icache, dcache, btac, tlb).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: move plat_cpu_reset_early before SCTLR generic inits

Prior this change, some plat_cpu_reset_early() implementation discarded
the generic effect of CFG_SCTLR_ALIGNMENT_CHECK or execute-never su

core: move plat_cpu_reset_early before SCTLR generic inits

Prior this change, some plat_cpu_reset_early() implementation discarded
the generic effect of CFG_SCTLR_ALIGNMENT_CHECK or execute-never support.

To overcome the issue, call plat_cpu_reset_early() before generic init
of SCTLR.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-

plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: sm: add PSCI system suspend

Add __weak property for the function, developers
could have their own implementation.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Fori

core: arm: sm: add PSCI system suspend

Add __weak property for the function, developers
could have their own implementation.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix overlapping conditions of pagestore load areas

This change copies pagestore remaining part first, from any location to
its target destination before copying pagestore init part to target
d

core: fix overlapping conditions of pagestore load areas

This change copies pagestore remaining part first, from any location to
its target destination before copying pagestore init part to target
destination. This prevents pagestore init copy to corrupt pagestore
remaining part at the location where bootloader loaded it.

As bootloader can load pagestore data anywhere in RAM, it is possible
that it loads it into an area overlapping with the area allocated by
the core to store effective pagestore. To prevent this, use memmove()
to copy the data instead of memcpy().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: handle aborts in system mode

Switch to handle aborts in system mode in order to be able to give a
stack trace in case an abort occurs in the abort handler.

In a manner similar to the A

core: arm32: handle aborts in system mode

Switch to handle aborts in system mode in order to be able to give a
stack trace in case an abort occurs in the abort handler.

In a manner similar to the AArch64 implementation are abort and undef
mode stack pointers pointing to the struct thread_core_local of
corresponding cpu.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: optimize tee_pager_handle_fault()

Optimizes tee_pager_handle_fault() by using ICACHE_AREA_INVALIDATE
instead of ICACHE_INVALIDATE.

Reviewed-by: Etienne Carriere <etienne.carriere@linar

core: pager: optimize tee_pager_handle_fault()

Optimizes tee_pager_handle_fault() by using ICACHE_AREA_INVALIDATE
instead of ICACHE_INVALIDATE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: remove unneeded tlb invalidation

Removes one unneeded tlb invalidation when unhiding a page. Since the page
was hidden there's no valid mapping for that entry and tlb entries can't
have

core: pager: remove unneeded tlb invalidation

Removes one unneeded tlb invalidation when unhiding a page. Since the page
was hidden there's no valid mapping for that entry and tlb entries can't
have been created.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mmu: enable MEM_AREA_TEE_COHERENT

Enable MEM_AREA_TEE_COHERENT with attribute setting to
SECURE/PRWX/NONCACHE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jen

core: arm: mmu: enable MEM_AREA_TEE_COHERENT

Enable MEM_AREA_TEE_COHERENT with attribute setting to
SECURE/PRWX/NONCACHE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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benchmark: fix core data-abort at address 0x0

Issue reproduces with enabled CFG_TEE_BENCHMARK and in case when
registration of benchmark timestamp buffer failes or isn't performed
(in case if any CA

benchmark: fix core data-abort at address 0x0

Issue reproduces with enabled CFG_TEE_BENCHMARK and in case when
registration of benchmark timestamp buffer failes or isn't performed
(in case if any CA is invoked directly, without using benchmark CA)

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores

Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores ARM SoCs.

plat-rockchip support features:
1.Support SMP cpu boot up and power down;
2.Support system reset;
3.Support GIC driver initialization.

make PLATFORM=rockchip-rk322x

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jero

core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three prope

core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three properties "device_type",
"reg" and "initial-mapped-area".

When prase the memory node, need to use the address/size-cells of
root node.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xt

plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xtest 4002 (s)
---------+--------------------
512 KiB | 16
544 KiB | 6
640 KiB | 0.07

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L

core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L1 data
cache

To A7 and A15, they both support coherent walk, see ID_MMFR3:
Updates to the translation tables do not require a clean to the point of
unification to ensure visibility by subsequent translation table walks

Note: I did not find doc talking coherent walk for A8, so A8 may need
cached flushed when update TLB?

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabili

drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.

Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.

The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.mk: export-ta_arm32: Set default value for CROSS_COMPILE

When building 32-bit optee_os, CROSS_COMPILE32 defaults to CROSS_COMPILE
if not set, and CROSS_COMPILE defaults to arm-linux-gnueabihf- i

arm.mk: export-ta_arm32: Set default value for CROSS_COMPILE

When building 32-bit optee_os, CROSS_COMPILE32 defaults to CROSS_COMPILE
if not set, and CROSS_COMPILE defaults to arm-linux-gnueabihf- if not
set.

When building 32-bit optee_test, CROSS_COMPILE32 also defaults to
CROSS_COMPILE if not set, but if CROSS_COMPILE is not set, there is no
default value, causing the native compiler to be used and generating
errors and confusion.

This patch makes the behavior and expectations consistent across both
optee_os and optee_test.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: Set default value for CONSOLE_UART_BASE in conf.mk

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB of LPDDR4 SDRAM memory, 32GB of UFS 2.0 flash
storage, and the latest generation Mali G71 MP8 graphics processor.

See https://www.96boards.org/product/hikey960 for more details.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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