plat-totalcompute: Add support for S-EL2 SPMC

This patch adds CFG_CORE_SEL2_SPMC support. Defines CFG_TZDRAM_START
address with memory region reserved for SPMC. Adds secondary cpu boot
request handl

plat-totalcompute: Add support for S-EL2 SPMC

This patch adds CFG_CORE_SEL2_SPMC support. Defines CFG_TZDRAM_START
address with memory region reserved for SPMC. Adds secondary cpu boot
request handler. Disables configuring GIC if SEL2 SPMC is enabled.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: Add OP-TEE SP manifest file

Add Secure Partition manifest file. This file is used when OP-TEE is build
with CFG_CORE_SEL2_SPMC support when creating the SP binary image.

Signed-o

plat-totalcompute: Add OP-TEE SP manifest file

Add Secure Partition manifest file. This file is used when OP-TEE is build
with CFG_CORE_SEL2_SPMC support when creating the SP binary image.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: define tzdram start address for S-EL1 SPMC config

Define TZDRAM_START for CFG_CORE_SEL1_SPMC config

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-

plat-totalcompute: define tzdram start address for S-EL1 SPMC config

Define TZDRAM_START for CFG_CORE_SEL1_SPMC config

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: Total Compute platform support

Initial support for Total Compute platform[1]
- defines tc0 platform configuration
- enables CFG_ARM64_core by default
- defines TZCDRAM_BASE

L

core: arm: Total Compute platform support

Initial support for Total Compute platform[1]
- defines tc0 platform configuration
- enables CFG_ARM64_core by default
- defines TZCDRAM_BASE

Link: [1] https://community.arm.com/developer/tools-software/oss-platforms/w/docs/606/total-compute

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Si

core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it t

plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it to 256kB which is reasonable for that platform.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_per

plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_periph’:
core/arch/arm/plat-stm32mp1/shared_resources.c:212:24: warning: implicit conversion from ‘enum shres_state’ to ‘enum stm32mp_shres’ [-Wenum-conversion]
212 | shres2str_state(state));
| ^~~~~

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: er

core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: error -3

i.MX device trees compiled with _symbols_ nodes makes DTB bigger than 56KiB.
Increase the CFG_DTB_MAX_SIZE from 56KiB to 128KiB for all imx6 and imx7
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerom

plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-o

plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-otx2t96
2. Passed xtest

Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-imx: registers: i2c: support i2c4

Add required definitions to support i2c4

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: D

plat-imx: registers: i2c: support i2c4

Add required definitions to support i2c4

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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plat-imx: registers: imx6: fix i2c3 base address

Fix the base address of the I2C3 controller

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadig

plat-imx: registers: imx6: fix i2c3 base address

Fix the base address of the I2C3 controller

Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Devendra Devadiga <devendradevadiga01@gmail.com>

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core: plat-ls: generate tee-raw.bin

LS Platforms use RAW OP-TEE binary, but it is not getting
generated by default for platforms.
So added code for generating it by default for LS platforms.

Signed

core: plat-ls: generate tee-raw.bin

LS Platforms use RAW OP-TEE binary, but it is not getting
generated by default for platforms.
So added code for generating it by default for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>

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core: clear temporary stack flag before entering boot_init_primary_late()

boot_init_primary_late() uses the stack of thread 0, so the flag that
indicates usage of the temporary stack must be cleared

core: clear temporary stack flag before entering boot_init_primary_late()

boot_init_primary_late() uses the stack of thread 0, so the flag that
indicates usage of the temporary stack must be cleared in the current
core's thread_core_local structure.

Fixes the following crash when CFG_CORE_DEBUG_CHECK_STACKS=y:

D/TC:0 0 select_vector:1126 SMCCC_ARCH_WORKAROUND_1 (0x80008000) available
D/TC:0 0 select_vector:1128 SMC Workaround for CVE-2017-5715 used
D/TC:0 0 check_stack_limits:370 Stack pointer out of range (0xb7f54fd0)
D/TC:0 0 print_stack_limits:346 tmp [0] 0xb7f57c90..0xb7f584b0
D/TC:0 0 print_stack_limits:346 tmp [1] 0xb7f58ad0..0xb7f592f0
D/TC:0 0 print_stack_limits:346 tmp [2] 0xb7f59910..0xb7f5a130
D/TC:0 0 print_stack_limits:346 tmp [3] 0xb7f5a750..0xb7f5af70
D/TC:0 0 print_stack_limits:351 abt [0] 0xb7f4e710..0xb7f4f330
D/TC:0 0 print_stack_limits:351 abt [1] 0xb7f4f950..0xb7f50570
D/TC:0 0 print_stack_limits:351 abt [2] 0xb7f50b90..0xb7f517b0
D/TC:0 0 print_stack_limits:351 abt [3] 0xb7f51dd0..0xb7f529f0
D/TC:0 0 print_stack_limits:356 thr [0] 0xb7f53030..0xb7f55030
D/TC:0 0 print_stack_limits:356 thr [1] 0xb7f55670..0xb7f57670
E/TC:0 0 Panic at core/arch/arm/kernel/thread.c:372 <check_stack_limits>

Fixes: 59ac3801b756 ("core: split boot_init_primary()")
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: use adr_l to reference stack_tmp_stride

When CFG_NUM_THREADS and/or CFG_TEE_CORE_NB_CORE become large enough,
link errors are reported:

$ make -s CFG_TEE_CORE_NB_CORE=48 CFG_NUM_THREA

core: arm64: use adr_l to reference stack_tmp_stride

When CFG_NUM_THREADS and/or CFG_TEE_CORE_NB_CORE become large enough,
link errors are reported:

$ make -s CFG_TEE_CORE_NB_CORE=48 CFG_NUM_THREADS=48 \
PLATFORM=vexpress-qemu_armv8a
out/arm-plat-vexpress/core/arch/arm/kernel/entry_a64.o: in function `clear_bss':
core/arch/arm/kernel/entry_a64.S:160:(.text._start+0x98): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `stack_tmp_stride' defined in .identity_map.stack_tmp_stride section in out/arm-plat-vexpress/core/arch/arm/kernel/thread.o
out/arm-plat-vexpress/core/arch/arm/kernel/entry_a64.o: in function `cpu_on_handler':
core/arch/arm/kernel/entry_a64.S:443:(.text.cpu_on_handler+0x50): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `stack_tmp_stride' defined in .identity_map.stack_tmp_stride section in out/arm-plat-vexpress/core/arch/arm/kernel/thread.o

Fix the issue by replacing the addr instruction with the adr_l macro.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: entry_a64.S: use adr_l macro instead of open coding

Replace the open-coded adrp + add :lo12: in set_sp with the macro that
does the very same thing (adr_l).

Signed-off-by: Jerome Forissier <j

core: entry_a64.S: use adr_l macro instead of open coding

Replace the open-coded adrp + add :lo12: in set_sp with the macro that
does the very same thing (adr_l).

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mm: split mobj_tee_ram onto rw/rx parts

Now mobj_tee_ram memory abstraction contains both TEE_RAM_RX and TEE_RAM_RW
regions joined together. This patch splits it to mobj_tee_ram_rx and
mobj_tee_ram_

mm: split mobj_tee_ram onto rw/rx parts

Now mobj_tee_ram memory abstraction contains both TEE_RAM_RX and TEE_RAM_RW
regions joined together. This patch splits it to mobj_tee_ram_rx and
mobj_tee_ram_rw to manage RX/RW memory objects separately.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>

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hikey, hikey960: disable CFG_SECURE_DATA_PATH by default

Since linaro-swg/linux.git branch optee [1] was rebased onto kernel
v5.12, Secure Data Path is broken in xtest [2] because the client side
is

hikey, hikey960: disable CFG_SECURE_DATA_PATH by default

Since linaro-swg/linux.git branch optee [1] was rebased onto kernel
v5.12, Secure Data Path is broken in xtest [2] because the client side
is based on the ION allocator, which was removed from the kernel.

Therefore, disable SDP support by default.

Link: [1] https://github.com/linaro-swg/linux/tree/optee-v5.12-20210628
Link: [2] https://github.com/OP-TEE/optee_test/blob/3.13.0/host/xtest/regression_1000.c#L1220-L1263
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: csu: RNGB TZ reservation on imx6ull/sl/sll

Reserve the RNGB to the TrustZone.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutron

drivers: csu: RNGB TZ reservation on imx6ull/sl/sll

Reserve the RNGB to the TrustZone.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>

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core: separate sp_ops using a __weak attribute instead

Breaks the dependency chain for sp_ops using the standard method with a
__weak symbol and an overriding symbol in link_dummies_paged.c.

Review

core: separate sp_ops using a __weak attribute instead

Breaks the dependency chain for sp_ops using the standard method with a
__weak symbol and an overriding symbol in link_dummies_paged.c.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU, pager, Clang 12)
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: separate stmm_sp_ops using a __weak attribute instead

Breaks the dependency chain for stmm_sp_ops using the standard method
with a __weak symbol and an overriding symbol in link_dummies_paged.

core: separate stmm_sp_ops using a __weak attribute instead

Breaks the dependency chain for stmm_sp_ops using the standard method
with a __weak symbol and an overriding symbol in link_dummies_paged.c.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: separate user_ta_ops using a __weak attribute instead

Breaks the dependency chain for user_ta_ops using the standard method
with a __weak symbol and an overriding symbol in link_dummies_paged.

core: separate user_ta_ops using a __weak attribute instead

Breaks the dependency chain for user_ta_ops using the standard method
with a __weak symbol and an overriding symbol in link_dummies_paged.c.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make __wq_rpc() static again

With dependency chains properly broken for various ops structs we can
make __wq_rpc() static again and remove it from link_dummies_paged.c.

Acked-by: Jerome Foris

core: make __wq_rpc() static again

With dependency chains properly broken for various ops structs we can
make __wq_rpc() static again and remove it from link_dummies_paged.c.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make __rodata_unpaged() symbols __weak

Makes the __rodata_unpaged tagged symbols __weak and non-static in order
to be overridden in core/arch/arm/kernel/link_dummies_paged.c. This
makes sure t

core: make __rodata_unpaged() symbols __weak

Makes the __rodata_unpaged tagged symbols __weak and non-static in order
to be overridden in core/arch/arm/kernel/link_dummies_paged.c. This
makes sure that these symbols doesn't bring in further symbols in the
unpaged section.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use separate sections for each __rodata_unpaged variable

Adds a mandatory argument to the macro __rodata_unpaged() to take the
name of the variable to put in the unpaged rodata section. This w

core: use separate sections for each __rodata_unpaged variable

Adds a mandatory argument to the macro __rodata_unpaged() to take the
name of the variable to put in the unpaged rodata section. This will
result in separate sections for each such variable and make it easier to
debug the pruning of the dependency tree for unpaged sections.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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