plat-stm32mp1: pmic: release constraint on non-secure I2C clock parent

Remove constraints securing the parents of a non-secure clock.
This constraints adds no value on such unsafe configuration.

Si

plat-stm32mp1: pmic: release constraint on non-secure I2C clock parent

Remove constraints securing the parents of a non-secure clock.
This constraints adds no value on such unsafe configuration.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: fix typo in parent clock trace string ID

Fix debug string identifier for parent clock HCLK6.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <j

plat-stm32mp1: fix typo in parent clock trace string ID

Fix debug string identifier for parent clock HCLK6.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: fix clock rate computation for CRYP1/GPIOZ/HASH1/MDMA

Fix parent clock identifier in stm32mp15 clock driver for CRYP1, GPIOZ,
HASH1 and MDMA clocks. The issue affected only clock rate

plat-stm32mp1: fix clock rate computation for CRYP1/GPIOZ/HASH1/MDMA

Fix parent clock identifier in stm32mp15 clock driver for CRYP1, GPIOZ,
HASH1 and MDMA clocks. The issue affected only clock rate computation
for these 4 clocks, not the clock gating support.

CRYP1, GPIOZ and HASH1 clocks are fed by HCLK5, not PCLK5. MDMA clock
is fed by HCLK6, not PCLK5.

Reported-by: Chaemin Lim <vn.cmlim@gmail.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move debug info and CC optimization level to config.mk

Move configuration switches CFG_DEBUG_INFO and CFG_CC_OPT_LEVEL
default values from arm.mk to config.mk and add a short description.

Sig

core: move debug info and CC optimization level to config.mk

Move configuration switches CFG_DEBUG_INFO and CFG_CC_OPT_LEVEL
default values from arm.mk to config.mk and add a short description.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: remove deprecated CFG_CC_OPTIMIZE_FOR_SIZE

Remove CFG_CC_OPTIMIZE_FOR_SIZE configuration size that is not used
and is incorrectly tested here (should be tested against != y).

Signed-off-

core: arm: remove deprecated CFG_CC_OPTIMIZE_FOR_SIZE

Remove CFG_CC_OPTIMIZE_FOR_SIZE configuration size that is not used
and is incorrectly tested here (should be tested against != y).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: enable CFG_ENABLE_EMBEDDED_TESTS by default

The vexpress platform family is mainly used for development and testing
so it makes sense to enable internal tests by default. What this do

plat-vexpress: enable CFG_ENABLE_EMBEDDED_TESTS by default

The vexpress platform family is mainly used for development and testing
so it makes sense to enable internal tests by default. What this does
currently is xtest 1001 runs core internal tests and xtest 1006 runs
TA bget tests.

As a result, remove redundant CFG_ENABLE_EMBEDDED_TESTS=y in the Azure
CI build script and add one configuration with tests disabled.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: new config switch CFG_PREALLOC_RPC_CACHE

CFG_PREALLOC_RPC_CACHE=y enables preallocation of an RPC shared memory
reference per secure thread. It is default enabled for backward
configuration co

core: new config switch CFG_PREALLOC_RPC_CACHE

CFG_PREALLOC_RPC_CACHE=y enables preallocation of an RPC shared memory
reference per secure thread. It is default enabled for backward
configuration compatibility.

Disabling CFG_PREALLOC_RPC_CACHE can be useful when CFG_WITH_PAGER=y
and the pager page pool is somewhat small as RPC cache shm consumes
several kByte of unpaged memory.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: arm: mm: add pager constraint on dynamic shm release functions

Fix missing pager constraints on dynamic shm release function. These
are needed since SMC function ID OPTEE_SMC_DISABLE_SHM_CACHE

core: arm: mm: add pager constraint on dynamic shm release functions

Fix missing pager constraints on dynamic shm release function. These
are needed since SMC function ID OPTEE_SMC_DISABLE_SHM_CACHE executes
in a fastcall SMC unpaged context and may call dynamic shm release
functions to release RPC preallocated shm.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx: add OCOTP driver

Add OCOTP driver for imx6, imx7, imx7ulp and imx8m platforms.
The implementation only supports the read of OCOTP shadow registers.
It also implements the tee_otp_get_d

drivers: imx: add OCOTP driver

Add OCOTP driver for imx6, imx7, imx7ulp and imx8m platforms.
The implementation only supports the read of OCOTP shadow registers.
It also implements the tee_otp_get_die_id() function.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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poplar: disable CFG_SECURE_DATA_PATH by default

Since linaro-swg/linux.git branch optee [1] was rebased onto kernel
v5.12, Secure Data Path is broken in xtest [2] because the client side
is based on

poplar: disable CFG_SECURE_DATA_PATH by default

Since linaro-swg/linux.git branch optee [1] was rebased onto kernel
v5.12, Secure Data Path is broken in xtest [2] because the client side
is based on the ION allocator, which was removed from the kernel.

Therefore, disable SDP support by default.

Link: [1] https://github.com/linaro-swg/linux/tree/optee-v5.12-20210628
Link: [2] https://github.com/OP-TEE/optee_test/blob/3.13.0/host/xtest/regression_1000.c#L1220-L1263

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: imx: disable SNVS for imx8qx

Disable SNVS as it is not supported by i.MX8QX platforms.

Fixes: d3bf580a67 ("core: imx: add support for i.MX 8QxP")
Signed-off-by: Clement Faure <clement.faure@n

core: imx: disable SNVS for imx8qx

Disable SNVS as it is not supported by i.MX8QX platforms.

Fixes: d3bf580a67 ("core: imx: add support for i.MX 8QxP")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: workaround PL310 errata 752271

Under very rare circumstances and under the following conditions, the
double linefill can cause data corruption.

Conditions:
* The double linefill feature

core: imx: workaround PL310 errata 752271

Under very rare circumstances and under the following conditions, the
double linefill can cause data corruption.

Conditions:
* The double linefill feature is enabled.
* The L2 cache contains dirty data.

This fault is present in PL310 revisions r3p0, r3p1, r3p1-50rel0.
This fault is fixed in r3p2.

The only workaround to this errata is to disable the double linefill
feature. [1]

Link: [1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: tune PL310 configuration for mx6sll

Tune PL310 L2 cache controller for better performances:
* Enable double linefill
* Disable prefetch drop
* Set prefetch offset to 0xF

Fixes: 4dac83

core: imx: tune PL310 configuration for mx6sll

Tune PL310 L2 cache controller for better performances:
* Enable double linefill
* Disable prefetch drop
* Set prefetch offset to 0xF

Fixes: 4dac83288 ("core: imx: add imx6sll evk board support")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: enable CFG_NO_SMP for imx6sll

i.MX 6SLL does not have SMP extension.

Fixes: 4dac83288b ("core: imx: add imx6sll evk board support")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
A

core: imx: enable CFG_NO_SMP for imx6sll

i.MX 6SLL does not have SMP extension.

Fixes: 4dac83288b ("core: imx: add imx6sll evk board support")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: remove useless header include

Remove #include <arm32.h> since arm.h is already included.

Fixes: f51f270a70 ("core: arm: imx: get mmdc type")
Signed-off-by: Clement Faure <clement.faure@n

core: imx: remove useless header include

Remove #include <arm32.h> since arm.h is already included.

Fixes: f51f270a70 ("core: arm: imx: get mmdc type")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: imx: crypto_conf: i.mx 7ulp does not support CAAM PKHA

There is no support for CAAM PKHA in i.MX 7ULP SOC.

Fixes: c3d61ba ("core: imx: Add imx7ulp evk board support")
Signed-off-by: Silvano d

core: imx: crypto_conf: i.mx 7ulp does not support CAAM PKHA

There is no support for CAAM PKHA in i.MX 7ULP SOC.

Fixes: c3d61ba ("core: imx: Add imx7ulp evk board support")
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: rework digprog driver

Rework digprog read value for all i.MX platforms.
Add the distinction between i.MX8MQ B0 and B1 platforms.
Add soc_is_*() functions for all i.MX8mscale platforms.

F

core: imx: rework digprog driver

Rework digprog read value for all i.MX platforms.
Add the distinction between i.MX8MQ B0 and B1 platforms.
Add soc_is_*() functions for all i.MX8mscale platforms.

Fixes: 247f081a95 ("core: imx: re-work SoC version detection")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: introduce CFG_MX8M compilation flag

Introduce the CFG_MX8M compilation flag that designates the following
platforms:
* mx8mmevk
* mx8mnevk
* mx8mpevk
* mx8mqevk
It is used to define c

core: imx: introduce CFG_MX8M compilation flag

Introduce the CFG_MX8M compilation flag that designates the following
platforms:
* mx8mmevk
* mx8mnevk
* mx8mpevk
* mx8mqevk
It is used to define code and features common to i.MX8mscale
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-ls: conf.mk: correct Embedded DTB flag

Emebedded DTB flag is CFG_EMBED_DTB which was wrongly
set as CFG_EMBED_DT.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carri

plat-ls: conf.mk: correct Embedded DTB flag

Emebedded DTB flag is CFG_EMBED_DTB which was wrongly
set as CFG_EMBED_DT.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: remove useless function in sam_pl310.c

l2_sram_config() is currently only used to set L2 SRAM for L2 cache.
Remove it and use io_write32() directly.

Signed-off-by: Clément Léger <clement.

plat-sam: remove useless function in sam_pl310.c

l2_sram_config() is currently only used to set L2 SRAM for L2 cache.
Remove it and use io_write32() directly.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: move pl310 related code to its own file

Cleanup main.c by moving pl310 code to sam_pl310.c file.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerom

plat-sam: move pl310 related code to its own file

Cleanup main.c by moving pl310 code to sam_pl310.c file.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: move secure zone to 0x20000000

Since DRAM size can vary depending on the platforms, 0x30000000 won't
work for some of them (sama5d27_som1_ek for instance with only 128Mb of
DRAM).
Move OP-

plat-sam: move secure zone to 0x20000000

Since DRAM size can vary depending on the platforms, 0x30000000 won't
work for some of them (sama5d27_som1_ek for instance with only 128Mb of
DRAM).
Move OP-TEE secure zone to 0x20000000 which will work for all devices.
During these changes, remove the possibility to override TZDRAM address
and size because since matrix configuration can't be changed easily, it
makes no sense to allow modifying them.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: switch to generic_ram_layout.h

Remove existing defines from platform_config.h to use generic ram layout
instead.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome

plat-sam: switch to generic_ram_layout.h

Remove existing defines from platform_config.h to use generic ram layout
instead.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: rename peripheral security function

Use more relevant names for peripheral security configuration function.
Indeed these functions set the peripherals as non-secure. Since
checkpatch warne

plat-sam: rename peripheral security function

Use more relevant names for peripheral security configuration function.
Indeed these functions set the peripherals as non-secure. Since
checkpatch warned that extern is unnecessary in header, remove it.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: set correct name for ID 1 which is PMC

AT91_ID_1 is in fact referring to the power management controller (PMC).
Replace it with AT91_ID_PMC.

Signed-off-by: Clément Léger <clement.leger@bo

plat-sam: set correct name for ID 1 which is PMC

AT91_ID_1 is in fact referring to the power management controller (PMC).
Replace it with AT91_ID_PMC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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