1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 30CFG_KERN_LINKER_ARCH ?= aarch64 31# TCR_EL1.IPS needs to be initialized according to the largest physical 32# address that we need to map. 33# Physical address size 34# 32 bits, 4GB. 35# 36 bits, 64GB. 36# (etc.) 37CFG_CORE_ARM64_PA_BITS ?= 32 38else 39ifeq ($(CFG_ARM32_core),y) 40CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 41CFG_KERN_LINKER_ARCH ?= arm 42else 43$(error Error: CFG_ARM64_core or CFG_ARM32_core should be defined) 44endif 45endif 46 47ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 48# Use hard-float for floating point support in user TAs instead of 49# soft-float 50CFG_WITH_VFP ?= y 51ifeq ($(CFG_ARM64_core),y) 52# AArch64 has no fallback to soft-float 53$(call force,CFG_WITH_VFP,y) 54endif 55ifeq ($(CFG_WITH_VFP),y) 56arm64-platform-hard-float-enabled := y 57ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 58arm32-platform-hard-float-enabled := y 59endif 60endif 61endif 62 63# Adds protection against CVE-2017-5715 also know as Spectre 64# (https://spectreattack.com) 65# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 66# Variant 2 67CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 68# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 69# secure EL0 instead of non-secure world. 70CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 71 72# Adds protection against a tool like Cachegrab 73# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 74# to prime and later analyze the L1D, L1I and BTB caches to gain 75# information from secure world execution. 76CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 77ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 78$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 79endif 80 81CFG_CORE_RWDATA_NOEXEC ?= y 82CFG_CORE_RODATA_NOEXEC ?= n 83ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 84$(call force,CFG_CORE_RWDATA_NOEXEC,y) 85endif 86# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 87CFG_SCTLR_ALIGNMENT_CHECK ?= n 88 89ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 90$(call force,CFG_WITH_LPAE,y) 91endif 92 93# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 94# that is, OP-TEE. 95# Note that this is an experimental feature, ABIs etc may have incompatible 96# changes 97ifeq ($(CFG_CORE_SEL1_SPMC),y) 98$(call force,CFG_CORE_FFA,y) 99$(call force,CFG_CORE_SEL2_SPMC,n) 100endif 101# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 102# that is, the hypervisor sandboxing OP-TEE 103ifeq ($(CFG_CORE_SEL2_SPMC),y) 104$(call force,CFG_CORE_FFA,y) 105endif 106 107# Unmaps all kernel mode code except the code needed to take exceptions 108# from user space and restore kernel mode mapping again. This gives more 109# strict control over what is accessible while in user mode. 110# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 111CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 112 113# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 114# save/restore PMCR during world switch. 115CFG_SM_NO_CYCLE_COUNTING ?= y 116 117ifeq ($(CFG_ARM32_core),y) 118# Configration directive related to ARMv7 optee boot arguments. 119# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 120# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 121# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 122endif 123 124core-platform-cppflags += -I$(arch-dir)/include 125core-platform-subdirs += \ 126 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 127 128ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 129core-platform-subdirs += $(arch-dir)/sm 130endif 131 132arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 133arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 134 135platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 136platform-aflags-generic ?= -pipe 137 138arm32-platform-aflags += -marm 139 140arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 141arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 142arm32-platform-cflags-generic-thumb ?= -mthumb \ 143 -fno-short-enums -fno-common -mno-unaligned-access 144arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 145 -fno-short-enums -fno-common -mno-unaligned-access 146arm32-platform-aflags-no-hard-float ?= 147 148arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 149arm64-platform-cflags-hard-float ?= 150arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 151 152ifeq ($(DEBUG),1) 153# For backwards compatibility 154$(call force,CFG_CC_OPT_LEVEL,0) 155$(call force,CFG_DEBUG_INFO,y) 156endif 157 158# Optimize for size by default, usually gives good performance too 159CFG_CC_OPT_LEVEL ?= s 160platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 161 162CFG_DEBUG_INFO ?= y 163ifeq ($(CFG_DEBUG_INFO),y) 164platform-cflags-debug-info ?= -g3 165platform-aflags-debug-info ?= -g 166endif 167 168core-platform-cflags += $(platform-cflags-optimization) 169core-platform-cflags += $(platform-cflags-generic) 170core-platform-cflags += $(platform-cflags-debug-info) 171 172core-platform-aflags += $(platform-aflags-generic) 173core-platform-aflags += $(platform-aflags-debug-info) 174 175ifeq ($(CFG_CORE_ASLR),y) 176core-platform-cflags += -fpie 177endif 178 179ifeq ($(CFG_ARM64_core),y) 180core-platform-cppflags += $(arm64-platform-cppflags) 181core-platform-cflags += $(arm64-platform-cflags) 182core-platform-cflags += $(arm64-platform-cflags-generic) 183core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 184core-platform-aflags += $(arm64-platform-aflags) 185else 186core-platform-cppflags += $(arm32-platform-cppflags) 187core-platform-cflags += $(arm32-platform-cflags) 188core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 189ifeq ($(CFG_UNWIND),y) 190core-platform-cflags += -funwind-tables 191endif 192ifeq ($(CFG_SYSCALL_FTRACE),y) 193core-platform-cflags += $(arm32-platform-cflags-generic-arm) 194else 195core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 196endif 197core-platform-aflags += $(core_arm32-platform-aflags) 198core-platform-aflags += $(arm32-platform-aflags) 199endif 200 201# Provide default supported-ta-targets if not set by the platform config 202ifeq (,$(supported-ta-targets)) 203supported-ta-targets = ta_arm32 204ifeq ($(CFG_ARM64_core),y) 205supported-ta-targets += ta_arm64 206endif 207endif 208 209ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 210unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 211ifneq (,$(unsup-targets)) 212$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 213endif 214 215ifneq ($(filter ta_arm32,$(ta-targets)),) 216# Variables for ta-target/sm "ta_arm32" 217CFG_ARM32_ta_arm32 := y 218arch-bits-ta_arm32 := 32 219ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 220ta_arm32-platform-cflags += $(arm32-platform-cflags) 221ta_arm32-platform-cflags += $(platform-cflags-optimization) 222ta_arm32-platform-cflags += $(platform-cflags-debug-info) 223ta_arm32-platform-cflags += -fpic 224 225# Thumb mode doesn't support function graph tracing due to missing 226# frame pointer support required to trace function call chain. So 227# rather compile in ARM mode if function tracing is enabled. 228ifeq ($(CFG_FTRACE_SUPPORT),y) 229ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 230else 231ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 232endif 233 234ifeq ($(arm32-platform-hard-float-enabled),y) 235ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 236else 237ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 238endif 239ifeq ($(CFG_UNWIND),y) 240ta_arm32-platform-cflags += -funwind-tables 241endif 242ta_arm32-platform-aflags += $(platform-aflags-generic) 243ta_arm32-platform-aflags += $(platform-aflags-debug-info) 244ta_arm32-platform-aflags += $(arm32-platform-aflags) 245 246ta_arm32-platform-cxxflags += -fpic 247ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 248ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 249ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 250 251ifeq ($(arm32-platform-hard-float-enabled),y) 252ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 253else 254ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 255endif 256 257ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 258ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 259ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 260ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 261ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 262 263ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 264ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 265ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 266ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 267ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 268ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 269endif 270 271ifneq ($(filter ta_arm64,$(ta-targets)),) 272# Variables for ta-target/sm "ta_arm64" 273CFG_ARM64_ta_arm64 := y 274arch-bits-ta_arm64 := 64 275ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 276ta_arm64-platform-cflags += $(arm64-platform-cflags) 277ta_arm64-platform-cflags += $(platform-cflags-optimization) 278ta_arm64-platform-cflags += $(platform-cflags-debug-info) 279ta_arm64-platform-cflags += -fpic 280ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 281ifeq ($(arm64-platform-hard-float-enabled),y) 282ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 283else 284ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 285endif 286ta_arm64-platform-aflags += $(platform-aflags-generic) 287ta_arm64-platform-aflags += $(platform-aflags-debug-info) 288ta_arm64-platform-aflags += $(arm64-platform-aflags) 289 290ta_arm64-platform-cxxflags += -fpic 291ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 292ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 293 294ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 295ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 296ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 297ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 298ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 299 300ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 301ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 302ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 303ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 304ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 305endif 306 307# Set cross compiler prefix for each TA target 308$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 309 310arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 311arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 312arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 313arm32-sysregs += $(arm32-sysreg-txt) 314 315ifeq ($(CFG_ARM_GICV3),y) 316arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 317arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 318arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 319arm32-sysregs += $(arm32-gicv3-sysreg-txt) 320endif 321 322arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 323 324define process-arm32-sysreg 325FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 326cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 327 328$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 329 @$(cmd-echo-silent) ' GEN $$@' 330 $(q)mkdir -p $$(dir $$@) 331 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 332 < $$< > $$@ 333 334FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 335cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 336 337$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 338 @$(cmd-echo-silent) ' GEN $$@' 339 $(q)mkdir -p $$(dir $$@) 340 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 341endef #process-arm32-sysreg 342 343$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 344