1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 #include <fdtdec.h> 12 13 #include "pinctrl-rockchip.h" 14 15 #define MAX_ROCKCHIP_PINS_ENTRIES 30 16 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 17 #define RK_FUNC_GPIO 0 18 19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 20 { 21 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 23 24 if (bank >= ctrl->nr_banks) { 25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 26 return -EINVAL; 27 } 28 29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 30 debug("pin conf pin %d >= %d\n", pin, 31 MAX_ROCKCHIP_GPIO_PER_BANK); 32 return -EINVAL; 33 } 34 35 return 0; 36 } 37 38 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 39 int *reg, u8 *bit, int *mask) 40 { 41 struct rockchip_pinctrl_priv *priv = bank->priv; 42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 43 struct rockchip_mux_recalced_data *data; 44 int i; 45 46 for (i = 0; i < ctrl->niomux_recalced; i++) { 47 data = &ctrl->iomux_recalced[i]; 48 if (data->num == bank->bank_num && 49 data->pin == pin) 50 break; 51 } 52 53 if (i >= ctrl->niomux_recalced) 54 return; 55 56 *reg = data->reg; 57 *mask = data->mask; 58 *bit = data->bit; 59 } 60 61 bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 62 int mux, u32 *reg, u32 *value) 63 { 64 struct rockchip_pinctrl_priv *priv = bank->priv; 65 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 66 struct rockchip_mux_route_data *data; 67 int i; 68 69 for (i = 0; i < ctrl->niomux_routes; i++) { 70 data = &ctrl->iomux_routes[i]; 71 if (data->bank_num == bank->bank_num && 72 data->pin == pin && data->func == mux) 73 break; 74 } 75 76 if (i >= ctrl->niomux_routes) 77 return false; 78 79 *reg = data->route_offset; 80 *value = data->route_val; 81 82 return true; 83 } 84 85 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) 86 { 87 int offset = 0; 88 89 if (mux_type & IOMUX_WIDTH_4BIT) { 90 if ((pin % 8) >= 4) 91 offset = 0x4; 92 *bit = (pin % 4) * 4; 93 *mask = 0xf; 94 } else if (mux_type & IOMUX_WIDTH_3BIT) { 95 /* 96 * pin0 ~ pin4 are at first register, and 97 * pin5 ~ pin7 are at second register. 98 */ 99 if ((pin % 8) >= 5) 100 offset = 0x4; 101 *bit = (pin % 8 % 5) * 3; 102 *mask = 0x7; 103 } else { 104 *bit = (pin % 8) * 2; 105 *mask = 0x3; 106 } 107 108 return offset; 109 } 110 111 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 112 { 113 struct rockchip_pinctrl_priv *priv = bank->priv; 114 int iomux_num = (pin / 8); 115 struct regmap *regmap; 116 unsigned int val; 117 int reg, ret, mask, mux_type; 118 u8 bit; 119 120 if (iomux_num > 3) 121 return -EINVAL; 122 123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 124 debug("pin %d is unrouted\n", pin); 125 return 0; 126 } 127 128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 129 return RK_FUNC_GPIO; 130 131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 132 ? priv->regmap_pmu : priv->regmap_base; 133 134 /* get basic quadrupel of mux registers and the correct reg inside */ 135 mux_type = bank->iomux[iomux_num].type; 136 reg = bank->iomux[iomux_num].offset; 137 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 138 139 if (bank->recalced_mask & BIT(pin)) 140 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 141 142 ret = regmap_read(regmap, reg, &val); 143 if (ret) 144 return ret; 145 146 return ((val >> bit) & mask); 147 } 148 149 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 150 int index) 151 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 152 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 153 154 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 155 } 156 157 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 158 int pin, int mux) 159 { 160 int iomux_num = (pin / 8); 161 162 if (iomux_num > 3) 163 return -EINVAL; 164 165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 166 debug("pin %d is unrouted\n", pin); 167 return -ENOTSUPP; 168 } 169 170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 171 if (mux != IOMUX_GPIO_ONLY) { 172 debug("pin %d only supports a gpio mux\n", pin); 173 return -ENOTSUPP; 174 } 175 } 176 177 return 0; 178 } 179 180 /* 181 * Set a new mux function for a pin. 182 * 183 * The register is divided into the upper and lower 16 bit. When changing 184 * a value, the previous register value is not read and changed. Instead 185 * it seems the changed bits are marked in the upper 16 bit, while the 186 * changed value gets set in the same offset in the lower 16 bit. 187 * All pin settings seem to be 2 bit wide in both the upper and lower 188 * parts. 189 * @bank: pin bank to change 190 * @pin: pin to change 191 * @mux: new mux function to set 192 */ 193 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 194 { 195 struct rockchip_pinctrl_priv *priv = bank->priv; 196 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 197 int iomux_num = (pin / 8); 198 int ret; 199 200 ret = rockchip_verify_mux(bank, pin, mux); 201 if (ret < 0) 202 return ret == -ENOTSUPP ? 0 : ret; 203 204 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 205 return 0; 206 207 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 208 209 if (!ctrl->set_mux) 210 return -ENOTSUPP; 211 212 ret = ctrl->set_mux(bank, pin, mux); 213 214 return ret; 215 } 216 217 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 218 { 2, 4, 8, 12, -1, -1, -1, -1 }, 219 { 3, 6, 9, 12, -1, -1, -1, -1 }, 220 { 5, 10, 15, 20, -1, -1, -1, -1 }, 221 { 4, 6, 8, 10, 12, 14, 16, 18 }, 222 { 4, 7, 10, 13, 16, 19, 22, 26 } 223 }; 224 225 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 226 int pin_num, int strength) 227 { 228 struct rockchip_pinctrl_priv *priv = bank->priv; 229 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 230 struct regmap *regmap; 231 int reg, ret, i; 232 u32 data, rmask_bits, temp; 233 u8 bit; 234 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 235 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 236 237 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 238 pin_num, strength); 239 240 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 241 242 ret = -EINVAL; 243 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 244 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 245 ret = i; 246 break; 247 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 248 ret = rockchip_perpin_drv_list[drv_type][i]; 249 break; 250 } 251 } 252 253 if (ret < 0) { 254 debug("unsupported driver strength %d\n", strength); 255 return ret; 256 } 257 258 switch (drv_type) { 259 case DRV_TYPE_IO_1V8_3V0_AUTO: 260 case DRV_TYPE_IO_3V3_ONLY: 261 rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; 262 switch (bit) { 263 case 0 ... 12: 264 /* regular case, nothing to do */ 265 break; 266 case 15: 267 /* 268 * drive-strength offset is special, as it is spread 269 * over 2 registers, the bit data[15] contains bit 0 270 * of the value while temp[1:0] contains bits 2 and 1 271 */ 272 data = (ret & 0x1) << 15; 273 temp = (ret >> 0x1) & 0x3; 274 275 data |= BIT(31); 276 ret = regmap_write(regmap, reg, data); 277 if (ret) 278 return ret; 279 280 temp |= (0x3 << 16); 281 reg += 0x4; 282 ret = regmap_write(regmap, reg, temp); 283 284 return ret; 285 case 18 ... 21: 286 /* setting fully enclosed in the second register */ 287 reg += 4; 288 bit -= 16; 289 break; 290 default: 291 debug("unsupported bit: %d for pinctrl drive type: %d\n", 292 bit, drv_type); 293 return -EINVAL; 294 } 295 break; 296 case DRV_TYPE_IO_DEFAULT: 297 case DRV_TYPE_IO_1V8_OR_3V0: 298 case DRV_TYPE_IO_1V8_ONLY: 299 rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; 300 break; 301 default: 302 debug("unsupported pinctrl drive type: %d\n", 303 drv_type); 304 return -EINVAL; 305 } 306 307 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 308 regmap_read(regmap, reg, &data); 309 data &= ~(((1 << rmask_bits) - 1) << bit); 310 } else { 311 /* enable the write to the equivalent lower bits */ 312 data = ((1 << rmask_bits) - 1) << (bit + 16); 313 } 314 315 data |= (ret << bit); 316 ret = regmap_write(regmap, reg, data); 317 return ret; 318 } 319 320 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 321 { 322 PIN_CONFIG_BIAS_DISABLE, 323 PIN_CONFIG_BIAS_PULL_UP, 324 PIN_CONFIG_BIAS_PULL_DOWN, 325 PIN_CONFIG_BIAS_BUS_HOLD 326 }, 327 { 328 PIN_CONFIG_BIAS_DISABLE, 329 PIN_CONFIG_BIAS_PULL_DOWN, 330 PIN_CONFIG_BIAS_DISABLE, 331 PIN_CONFIG_BIAS_PULL_UP 332 }, 333 }; 334 335 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 336 int pin_num, int pull) 337 { 338 struct rockchip_pinctrl_priv *priv = bank->priv; 339 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 340 struct regmap *regmap; 341 int reg, ret, i, pull_type; 342 u8 bit; 343 u32 data; 344 345 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 346 pin_num, pull); 347 348 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 349 350 switch (ctrl->type) { 351 case RK3036: 352 case RK3128: 353 data = BIT(bit + 16); 354 if (pull == PIN_CONFIG_BIAS_DISABLE) 355 data |= BIT(bit); 356 ret = regmap_write(regmap, reg, data); 357 break; 358 case RV1108: 359 case RK3188: 360 case RK3288: 361 case RK3368: 362 case RK3399: 363 /* 364 * Where need to clean the special mask for 365 * rockchip_pull_list. 366 */ 367 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 368 ret = -EINVAL; 369 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 370 i++) { 371 if (rockchip_pull_list[pull_type][i] == pull) { 372 ret = i; 373 break; 374 } 375 } 376 377 if (ret < 0) { 378 debug("unsupported pull setting %d\n", pull); 379 return ret; 380 } 381 382 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 383 regmap_read(regmap, reg, &data); 384 data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); 385 } else { 386 /* enable the write to the equivalent lower bits */ 387 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 388 } 389 390 data |= (ret << bit); 391 ret = regmap_write(regmap, reg, data); 392 break; 393 default: 394 debug("unsupported pinctrl type\n"); 395 return -EINVAL; 396 } 397 398 return ret; 399 } 400 401 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 402 int pin_num, int enable) 403 { 404 struct rockchip_pinctrl_priv *priv = bank->priv; 405 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 406 struct regmap *regmap; 407 int reg, ret; 408 u8 bit; 409 u32 data; 410 411 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 412 pin_num, enable); 413 414 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 415 if (ret) 416 return ret; 417 418 /* enable the write to the equivalent lower bits */ 419 data = BIT(bit + 16) | (enable << bit); 420 421 return regmap_write(regmap, reg, data); 422 } 423 424 /* 425 * Pinconf_ops handling 426 */ 427 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 428 unsigned int pull) 429 { 430 switch (ctrl->type) { 431 case RK3036: 432 case RK3128: 433 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 434 pull == PIN_CONFIG_BIAS_DISABLE); 435 case RV1108: 436 case RK3188: 437 case RK3288: 438 case RK3368: 439 case RK3399: 440 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 441 } 442 443 return false; 444 } 445 446 /* set the pin config settings for a specified pin */ 447 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 448 u32 pin, u32 param, u32 arg) 449 { 450 struct rockchip_pinctrl_priv *priv = bank->priv; 451 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 452 int rc; 453 454 switch (param) { 455 case PIN_CONFIG_BIAS_DISABLE: 456 rc = rockchip_set_pull(bank, pin, param); 457 if (rc) 458 return rc; 459 break; 460 461 case PIN_CONFIG_BIAS_PULL_UP: 462 case PIN_CONFIG_BIAS_PULL_DOWN: 463 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 464 case PIN_CONFIG_BIAS_BUS_HOLD: 465 if (!rockchip_pinconf_pull_valid(ctrl, param)) 466 return -ENOTSUPP; 467 468 if (!arg) 469 return -EINVAL; 470 471 rc = rockchip_set_pull(bank, pin, param); 472 if (rc) 473 return rc; 474 break; 475 476 case PIN_CONFIG_DRIVE_STRENGTH: 477 if (!ctrl->drv_calc_reg) 478 return -ENOTSUPP; 479 480 rc = rockchip_set_drive_perpin(bank, pin, arg); 481 if (rc < 0) 482 return rc; 483 break; 484 485 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 486 if (!ctrl->schmitt_calc_reg) 487 return -ENOTSUPP; 488 489 rc = rockchip_set_schmitt(bank, pin, arg); 490 if (rc < 0) 491 return rc; 492 break; 493 494 default: 495 break; 496 } 497 498 return 0; 499 } 500 501 static const struct pinconf_param rockchip_conf_params[] = { 502 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 503 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 504 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 505 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 506 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, 507 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 508 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 509 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 510 }; 511 512 static int rockchip_pinconf_prop_name_to_param(const char *property, 513 u32 *default_value) 514 { 515 const struct pinconf_param *p, *end; 516 517 p = rockchip_conf_params; 518 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 519 520 /* See if this pctldev supports this parameter */ 521 for (; p < end; p++) { 522 if (!strcmp(property, p->property)) { 523 *default_value = p->default_value; 524 return p->param; 525 } 526 } 527 528 *default_value = 0; 529 return -EPERM; 530 } 531 532 static int rockchip_pinctrl_set_state(struct udevice *dev, 533 struct udevice *config) 534 { 535 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 536 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 537 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 538 u32 bank, pin, mux, conf, arg, default_val; 539 int ret, count, i; 540 const char *prop_name; 541 const void *value; 542 int prop_len, param; 543 const u32 *data; 544 ofnode node; 545 #ifdef CONFIG_OF_LIVE 546 const struct device_node *np; 547 struct property *pp; 548 #else 549 int property_offset, pcfg_node; 550 const void *blob = gd->fdt_blob; 551 #endif 552 data = dev_read_prop(config, "rockchip,pins", &count); 553 if (count < 0) { 554 debug("%s: bad array size %d\n", __func__, count); 555 return -EINVAL; 556 } 557 558 count /= sizeof(u32); 559 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 560 debug("%s: unsupported pins array count %d\n", 561 __func__, count); 562 return -EINVAL; 563 } 564 565 for (i = 0; i < count; i++) 566 cells[i] = fdt32_to_cpu(data[i]); 567 568 for (i = 0; i < (count >> 2); i++) { 569 bank = cells[4 * i + 0]; 570 pin = cells[4 * i + 1]; 571 mux = cells[4 * i + 2]; 572 conf = cells[4 * i + 3]; 573 574 ret = rockchip_verify_config(dev, bank, pin); 575 if (ret) 576 return ret; 577 578 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 579 if (ret) 580 return ret; 581 582 node = ofnode_get_by_phandle(conf); 583 if (!ofnode_valid(node)) 584 return -ENODEV; 585 #ifdef CONFIG_OF_LIVE 586 np = ofnode_to_np(node); 587 for (pp = np->properties; pp; pp = pp->next) { 588 prop_name = pp->name; 589 prop_len = pp->length; 590 value = pp->value; 591 #else 592 pcfg_node = ofnode_to_offset(node); 593 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 594 value = fdt_getprop_by_offset(blob, property_offset, 595 &prop_name, &prop_len); 596 if (!value) 597 return -ENOENT; 598 #endif 599 param = rockchip_pinconf_prop_name_to_param(prop_name, 600 &default_val); 601 if (param < 0) 602 break; 603 604 if (prop_len >= sizeof(fdt32_t)) 605 arg = fdt32_to_cpu(*(fdt32_t *)value); 606 else 607 arg = default_val; 608 609 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 610 param, arg); 611 if (ret) { 612 debug("%s: rockchip_pinconf_set fail: %d\n", 613 __func__, ret); 614 return ret; 615 } 616 } 617 } 618 619 return 0; 620 } 621 622 static int rockchip_pinctrl_get_pins_count(struct udevice *dev) 623 { 624 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 625 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 626 627 return ctrl->nr_pins; 628 } 629 630 const struct pinctrl_ops rockchip_pinctrl_ops = { 631 .get_pins_count = rockchip_pinctrl_get_pins_count, 632 .set_state = rockchip_pinctrl_set_state, 633 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 634 }; 635 636 /* retrieve the soc specific data */ 637 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 638 { 639 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 640 struct rockchip_pin_ctrl *ctrl = 641 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 642 struct rockchip_pin_bank *bank; 643 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 644 645 grf_offs = ctrl->grf_mux_offset; 646 pmu_offs = ctrl->pmu_mux_offset; 647 drv_pmu_offs = ctrl->pmu_drv_offset; 648 drv_grf_offs = ctrl->grf_drv_offset; 649 bank = ctrl->pin_banks; 650 651 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 652 int bank_pins = 0; 653 654 bank->priv = priv; 655 bank->pin_base = ctrl->nr_pins; 656 ctrl->nr_pins += bank->nr_pins; 657 658 /* calculate iomux and drv offsets */ 659 for (j = 0; j < 4; j++) { 660 struct rockchip_iomux *iom = &bank->iomux[j]; 661 struct rockchip_drv *drv = &bank->drv[j]; 662 int inc; 663 664 if (bank_pins >= bank->nr_pins) 665 break; 666 667 /* preset iomux offset value, set new start value */ 668 if (iom->offset >= 0) { 669 if (iom->type & IOMUX_SOURCE_PMU) 670 pmu_offs = iom->offset; 671 else 672 grf_offs = iom->offset; 673 } else { /* set current iomux offset */ 674 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 675 pmu_offs : grf_offs; 676 } 677 678 /* preset drv offset value, set new start value */ 679 if (drv->offset >= 0) { 680 if (iom->type & IOMUX_SOURCE_PMU) 681 drv_pmu_offs = drv->offset; 682 else 683 drv_grf_offs = drv->offset; 684 } else { /* set current drv offset */ 685 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 686 drv_pmu_offs : drv_grf_offs; 687 } 688 689 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 690 i, j, iom->offset, drv->offset); 691 692 /* 693 * Increase offset according to iomux width. 694 * 4bit iomux'es are spread over two registers. 695 */ 696 inc = (iom->type & (IOMUX_WIDTH_4BIT | 697 IOMUX_WIDTH_3BIT)) ? 8 : 4; 698 if (iom->type & IOMUX_SOURCE_PMU) 699 pmu_offs += inc; 700 else 701 grf_offs += inc; 702 703 /* 704 * Increase offset according to drv width. 705 * 3bit drive-strenth'es are spread over two registers. 706 */ 707 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 708 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 709 inc = 8; 710 else 711 inc = 4; 712 713 if (iom->type & IOMUX_SOURCE_PMU) 714 drv_pmu_offs += inc; 715 else 716 drv_grf_offs += inc; 717 718 bank_pins += 8; 719 } 720 721 /* calculate the per-bank recalced_mask */ 722 for (j = 0; j < ctrl->niomux_recalced; j++) { 723 int pin = 0; 724 725 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 726 pin = ctrl->iomux_recalced[j].pin; 727 bank->recalced_mask |= BIT(pin); 728 } 729 } 730 731 /* calculate the per-bank route_mask */ 732 for (j = 0; j < ctrl->niomux_routes; j++) { 733 int pin = 0; 734 735 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 736 pin = ctrl->iomux_routes[j].pin; 737 bank->route_mask |= BIT(pin); 738 } 739 } 740 } 741 742 return ctrl; 743 } 744 745 int rockchip_pinctrl_probe(struct udevice *dev) 746 { 747 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 748 struct rockchip_pin_ctrl *ctrl; 749 struct udevice *syscon; 750 struct regmap *regmap; 751 int ret = 0; 752 753 /* get rockchip grf syscon phandle */ 754 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 755 &syscon); 756 if (ret) { 757 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 758 return ret; 759 } 760 761 /* get grf-reg base address */ 762 regmap = syscon_get_regmap(syscon); 763 if (!regmap) { 764 debug("unable to find rockchip grf regmap\n"); 765 return -ENODEV; 766 } 767 priv->regmap_base = regmap; 768 769 /* option: get pmu-reg base address */ 770 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 771 &syscon); 772 if (!ret) { 773 /* get pmugrf-reg base address */ 774 regmap = syscon_get_regmap(syscon); 775 if (!regmap) { 776 debug("unable to find rockchip pmu regmap\n"); 777 return -ENODEV; 778 } 779 priv->regmap_pmu = regmap; 780 } 781 782 ctrl = rockchip_pinctrl_get_soc_data(dev); 783 if (!ctrl) { 784 debug("driver data not available\n"); 785 return -EINVAL; 786 } 787 788 priv->ctrl = ctrl; 789 return 0; 790 } 791