1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 #include <fdtdec.h> 12 #include <dm/uclass-internal.h> 13 #include <asm/gpio.h> 14 15 #include "pinctrl-rockchip.h" 16 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 19 #define RK_FUNC_GPIO 0 20 21 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 22 { 23 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 24 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 25 26 if (bank >= ctrl->nr_banks) { 27 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 28 return -EINVAL; 29 } 30 31 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 32 debug("pin conf pin %d >= %d\n", pin, 33 MAX_ROCKCHIP_GPIO_PER_BANK); 34 return -EINVAL; 35 } 36 37 return 0; 38 } 39 40 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 41 int *reg, u8 *bit, int *mask) 42 { 43 struct rockchip_pinctrl_priv *priv = bank->priv; 44 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 45 struct rockchip_mux_recalced_data *data; 46 int i; 47 48 for (i = 0; i < ctrl->niomux_recalced; i++) { 49 data = &ctrl->iomux_recalced[i]; 50 if (data->num == bank->bank_num && 51 data->pin == pin) 52 break; 53 } 54 55 if (i >= ctrl->niomux_recalced) 56 return; 57 58 *reg = data->reg; 59 *mask = data->mask; 60 *bit = data->bit; 61 } 62 63 static enum rockchip_pin_route_type 64 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 65 int mux, u32 *reg, u32 *value) 66 { 67 struct rockchip_pinctrl_priv *priv = bank->priv; 68 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 69 struct rockchip_mux_route_data *data; 70 int i; 71 72 for (i = 0; i < ctrl->niomux_routes; i++) { 73 data = &ctrl->iomux_routes[i]; 74 if (data->bank_num == bank->bank_num && 75 data->pin == pin && data->func == mux) 76 break; 77 } 78 79 if (i >= ctrl->niomux_routes) 80 return ROUTE_TYPE_INVALID; 81 82 *reg = data->route_offset; 83 *value = data->route_val; 84 85 return data->route_type; 86 } 87 88 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) 89 { 90 int offset = 0; 91 92 if (mux_type & IOMUX_WIDTH_4BIT) { 93 if ((pin % 8) >= 4) 94 offset = 0x4; 95 *bit = (pin % 4) * 4; 96 *mask = 0xf; 97 } else if (mux_type & IOMUX_WIDTH_3BIT) { 98 /* 99 * pin0 ~ pin4 are at first register, and 100 * pin5 ~ pin7 are at second register. 101 */ 102 if ((pin % 8) >= 5) 103 offset = 0x4; 104 *bit = (pin % 8 % 5) * 3; 105 *mask = 0x7; 106 } else { 107 *bit = (pin % 8) * 2; 108 *mask = 0x3; 109 } 110 111 return offset; 112 } 113 114 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 115 { 116 struct rockchip_pinctrl_priv *priv = bank->priv; 117 int iomux_num = (pin / 8); 118 struct regmap *regmap; 119 unsigned int val; 120 int reg, ret, mask, mux_type; 121 u8 bit; 122 123 if (iomux_num > 3) 124 return -EINVAL; 125 126 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 127 debug("pin %d is unrouted\n", pin); 128 return -ENOTSUPP; 129 } 130 131 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 132 return RK_FUNC_GPIO; 133 134 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 135 ? priv->regmap_pmu : priv->regmap_base; 136 137 /* get basic quadrupel of mux registers and the correct reg inside */ 138 mux_type = bank->iomux[iomux_num].type; 139 reg = bank->iomux[iomux_num].offset; 140 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 141 142 if (bank->recalced_mask & BIT(pin)) 143 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 144 145 ret = regmap_read(regmap, reg, &val); 146 if (ret) 147 return ret; 148 149 return ((val >> bit) & mask); 150 } 151 152 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 153 int index) 154 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 155 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 156 157 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 158 } 159 160 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 161 int pin, int mux) 162 { 163 int iomux_num = (pin / 8); 164 165 if (iomux_num > 3) 166 return -EINVAL; 167 168 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 169 debug("pin %d is unrouted\n", pin); 170 return -ENOTSUPP; 171 } 172 173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 174 if (mux != IOMUX_GPIO_ONLY) { 175 debug("pin %d only supports a gpio mux\n", pin); 176 return -ENOTSUPP; 177 } 178 } 179 180 return 0; 181 } 182 183 /* 184 * Set a new mux function for a pin. 185 * 186 * The register is divided into the upper and lower 16 bit. When changing 187 * a value, the previous register value is not read and changed. Instead 188 * it seems the changed bits are marked in the upper 16 bit, while the 189 * changed value gets set in the same offset in the lower 16 bit. 190 * All pin settings seem to be 2 bit wide in both the upper and lower 191 * parts. 192 * @bank: pin bank to change 193 * @pin: pin to change 194 * @mux: new mux function to set 195 */ 196 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 197 { 198 struct rockchip_pinctrl_priv *priv = bank->priv; 199 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 200 int iomux_num = (pin / 8); 201 int ret; 202 203 ret = rockchip_verify_mux(bank, pin, mux); 204 if (ret < 0) 205 return ret == -ENOTSUPP ? 0 : ret; 206 207 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 208 return 0; 209 210 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 211 212 if (!ctrl->set_mux) 213 return -ENOTSUPP; 214 215 ret = ctrl->set_mux(bank, pin, mux); 216 if (ret) 217 return ret; 218 219 if (bank->route_mask & BIT(pin)) { 220 struct regmap *regmap; 221 u32 route_reg = 0, route_val = 0; 222 223 ret = rockchip_get_mux_route(bank, pin, mux, 224 &route_reg, &route_val); 225 switch (ret) { 226 case ROUTE_TYPE_DEFAULT: 227 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 228 regmap = priv->regmap_pmu; 229 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 230 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 231 else 232 regmap = priv->regmap_base; 233 234 regmap_write(regmap, route_reg, route_val); 235 break; 236 case ROUTE_TYPE_TOPGRF: 237 regmap_write(priv->regmap_base, route_reg, route_val); 238 break; 239 case ROUTE_TYPE_PMUGRF: 240 regmap_write(priv->regmap_pmu, route_reg, route_val); 241 break; 242 case ROUTE_TYPE_INVALID: /* Fall through */ 243 default: 244 break; 245 } 246 } 247 248 return 0; 249 } 250 251 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 252 { 2, 4, 8, 12, -1, -1, -1, -1 }, 253 { 3, 6, 9, 12, -1, -1, -1, -1 }, 254 { 5, 10, 15, 20, -1, -1, -1, -1 }, 255 { 4, 6, 8, 10, 12, 14, 16, 18 }, 256 { 4, 7, 10, 13, 16, 19, 22, 26 } 257 }; 258 259 int rockchip_translate_drive_value(int type, int strength) 260 { 261 int i, ret; 262 263 ret = -EINVAL; 264 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) { 265 if (rockchip_perpin_drv_list[type][i] == strength) { 266 ret = i; 267 break; 268 } else if (rockchip_perpin_drv_list[type][i] < 0) { 269 ret = rockchip_perpin_drv_list[type][i]; 270 break; 271 } 272 } 273 274 return ret; 275 } 276 277 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 278 int pin_num, int strength) 279 { 280 struct rockchip_pinctrl_priv *priv = bank->priv; 281 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 282 283 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 284 pin_num, strength); 285 286 if (!ctrl->set_drive) 287 return -ENOTSUPP; 288 289 return ctrl->set_drive(bank, pin_num, strength); 290 } 291 292 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 293 { 294 PIN_CONFIG_BIAS_DISABLE, 295 PIN_CONFIG_BIAS_PULL_UP, 296 PIN_CONFIG_BIAS_PULL_DOWN, 297 PIN_CONFIG_BIAS_BUS_HOLD 298 }, 299 { 300 PIN_CONFIG_BIAS_DISABLE, 301 PIN_CONFIG_BIAS_PULL_DOWN, 302 PIN_CONFIG_BIAS_DISABLE, 303 PIN_CONFIG_BIAS_PULL_UP 304 }, 305 }; 306 307 int rockchip_translate_pull_value(int type, int pull) 308 { 309 int i, ret; 310 311 ret = -EINVAL; 312 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]); 313 i++) { 314 if (rockchip_pull_list[type][i] == pull) { 315 ret = i; 316 break; 317 } 318 } 319 320 return ret; 321 } 322 323 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 324 int pin_num, int pull) 325 { 326 struct rockchip_pinctrl_priv *priv = bank->priv; 327 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 328 329 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 330 pin_num, pull); 331 332 if (!ctrl->set_pull) 333 return -ENOTSUPP; 334 335 return ctrl->set_pull(bank, pin_num, pull); 336 } 337 338 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 339 int pin_num, int enable) 340 { 341 struct rockchip_pinctrl_priv *priv = bank->priv; 342 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 343 344 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 345 pin_num, enable); 346 347 if (!ctrl->set_schmitt) 348 return -ENOTSUPP; 349 350 return ctrl->set_schmitt(bank, pin_num, enable); 351 } 352 353 /* set the pin config settings for a specified pin */ 354 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 355 u32 pin, u32 param, u32 arg) 356 { 357 int rc; 358 struct gpio_desc desc; 359 char gpio_name[16]; 360 361 switch (param) { 362 case PIN_CONFIG_BIAS_DISABLE: 363 case PIN_CONFIG_BIAS_PULL_UP: 364 case PIN_CONFIG_BIAS_PULL_DOWN: 365 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 366 case PIN_CONFIG_BIAS_BUS_HOLD: 367 rc = rockchip_set_pull(bank, pin, param); 368 if (rc) 369 return rc; 370 break; 371 372 case PIN_CONFIG_DRIVE_STRENGTH: 373 rc = rockchip_set_drive_perpin(bank, pin, arg); 374 if (rc < 0) 375 return rc; 376 break; 377 378 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 379 rc = rockchip_set_schmitt(bank, pin, arg); 380 if (rc < 0) 381 return rc; 382 break; 383 384 case PIN_CONFIG_OUTPUT: 385 desc.flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; 386 if (!arg) desc.flags |= GPIOD_ACTIVE_LOW; 387 snprintf(gpio_name, 16, "%s%d", bank->name, pin); 388 rc = dm_gpio_lookup_name(gpio_name, &desc); 389 if (rc < 0) { 390 debug("%s: GPIO %s-%d lookup failed (ret=%d)\n", __func__, 391 bank->name, pin, rc); 392 return rc; 393 } 394 395 rc = dm_gpio_request(&desc, gpio_name); 396 if (rc < 0) { 397 debug("%s: GPIO %s-%d request failed (ret=%d)\n", __func__, 398 bank->name, pin, rc); 399 return rc; 400 } 401 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); 402 dm_gpio_set_value(&desc, arg ? 1 : 0); 403 debug("%s: GPIO %s-%d set to %d\n", __func__, bank->name, pin, arg); 404 break; 405 default: 406 break; 407 } 408 409 return 0; 410 } 411 412 static const struct pinconf_param rockchip_conf_params[] = { 413 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 414 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 415 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 416 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 417 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, 418 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 419 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 420 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 421 { "output-high", PIN_CONFIG_OUTPUT, 1, }, 422 { "output-low", PIN_CONFIG_OUTPUT, 0, }, 423 }; 424 425 static int rockchip_pinconf_prop_name_to_param(const char *property, 426 u32 *default_value) 427 { 428 const struct pinconf_param *p, *end; 429 430 p = rockchip_conf_params; 431 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 432 433 /* See if this pctldev supports this parameter */ 434 for (; p < end; p++) { 435 if (!strcmp(property, p->property)) { 436 *default_value = p->default_value; 437 return p->param; 438 } 439 } 440 441 *default_value = 0; 442 return -EPERM; 443 } 444 445 static int rockchip_pinctrl_set_state(struct udevice *dev, 446 struct udevice *config) 447 { 448 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 449 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 450 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 451 u32 bank, pin, mux, conf, arg, default_val; 452 int ret, count, i; 453 const char *prop_name; 454 const void *value; 455 int prop_len, param; 456 const u32 *data; 457 ofnode node; 458 #if CONFIG_IS_ENABLED(OF_LIVE) 459 const struct device_node *np; 460 struct property *pp; 461 #else 462 int property_offset, pcfg_node; 463 const void *blob = gd->fdt_blob; 464 #endif 465 data = dev_read_prop(config, "rockchip,pins", &count); 466 if (count < 0) { 467 debug("%s: bad array size %d\n", __func__, count); 468 return -EINVAL; 469 } 470 471 count /= sizeof(u32); 472 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 473 debug("%s: unsupported pins array count %d\n", 474 __func__, count); 475 return -EINVAL; 476 } 477 478 for (i = 0; i < count; i++) 479 cells[i] = fdt32_to_cpu(data[i]); 480 481 for (i = 0; i < (count >> 2); i++) { 482 bank = cells[4 * i + 0]; 483 pin = cells[4 * i + 1]; 484 mux = cells[4 * i + 2]; 485 conf = cells[4 * i + 3]; 486 487 ret = rockchip_verify_config(dev, bank, pin); 488 if (ret) 489 return ret; 490 491 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 492 if (ret) 493 return ret; 494 495 node = ofnode_get_by_phandle(conf); 496 if (!ofnode_valid(node)) 497 return -ENODEV; 498 #if CONFIG_IS_ENABLED(OF_LIVE) 499 np = ofnode_to_np(node); 500 for (pp = np->properties; pp; pp = pp->next) { 501 prop_name = pp->name; 502 prop_len = pp->length; 503 value = pp->value; 504 #else 505 pcfg_node = ofnode_to_offset(node); 506 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 507 value = fdt_getprop_by_offset(blob, property_offset, 508 &prop_name, &prop_len); 509 if (!value) 510 return -ENOENT; 511 #endif 512 param = rockchip_pinconf_prop_name_to_param(prop_name, 513 &default_val); 514 if (param < 0) 515 break; 516 517 if (prop_len >= sizeof(fdt32_t)) 518 arg = fdt32_to_cpu(*(fdt32_t *)value); 519 else 520 arg = default_val; 521 522 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 523 param, arg); 524 if (ret) { 525 debug("%s: rockchip_pinconf_set fail: %d\n", 526 __func__, ret); 527 return ret; 528 } 529 } 530 } 531 532 return 0; 533 } 534 535 static int rockchip_pinctrl_get_pins_count(struct udevice *dev) 536 { 537 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 538 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 539 540 return ctrl->nr_pins; 541 } 542 543 const struct pinctrl_ops rockchip_pinctrl_ops = { 544 .get_pins_count = rockchip_pinctrl_get_pins_count, 545 .set_state = rockchip_pinctrl_set_state, 546 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 547 }; 548 549 /* retrieve the soc specific data */ 550 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 551 { 552 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 553 struct rockchip_pin_ctrl *ctrl = 554 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 555 struct rockchip_pin_bank *bank; 556 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 557 u32 nr_pins; 558 559 grf_offs = ctrl->grf_mux_offset; 560 pmu_offs = ctrl->pmu_mux_offset; 561 drv_pmu_offs = ctrl->pmu_drv_offset; 562 drv_grf_offs = ctrl->grf_drv_offset; 563 bank = ctrl->pin_banks; 564 565 nr_pins = 0; 566 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 567 int bank_pins = 0; 568 569 bank->priv = priv; 570 bank->pin_base = nr_pins; 571 nr_pins += bank->nr_pins; 572 573 /* calculate iomux and drv offsets */ 574 for (j = 0; j < 4; j++) { 575 struct rockchip_iomux *iom = &bank->iomux[j]; 576 struct rockchip_drv *drv = &bank->drv[j]; 577 int inc; 578 579 if (bank_pins >= nr_pins) 580 break; 581 582 /* preset iomux offset value, set new start value */ 583 if (iom->offset >= 0) { 584 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 585 pmu_offs = iom->offset; 586 else 587 grf_offs = iom->offset; 588 } else { /* set current iomux offset */ 589 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 590 (iom->type & IOMUX_L_SOURCE_PMU)) ? 591 pmu_offs : grf_offs; 592 } 593 594 /* preset drv offset value, set new start value */ 595 if (drv->offset >= 0) { 596 if (iom->type & IOMUX_SOURCE_PMU) 597 drv_pmu_offs = drv->offset; 598 else 599 drv_grf_offs = drv->offset; 600 } else { /* set current drv offset */ 601 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 602 drv_pmu_offs : drv_grf_offs; 603 } 604 605 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 606 i, j, iom->offset, drv->offset); 607 608 /* 609 * Increase offset according to iomux width. 610 * 4bit iomux'es are spread over two registers. 611 */ 612 inc = (iom->type & (IOMUX_WIDTH_4BIT | 613 IOMUX_WIDTH_3BIT | 614 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 615 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 616 pmu_offs += inc; 617 else 618 grf_offs += inc; 619 620 /* 621 * Increase offset according to drv width. 622 * 3bit drive-strenth'es are spread over two registers. 623 */ 624 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 625 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 626 inc = 8; 627 else 628 inc = 4; 629 630 if (iom->type & IOMUX_SOURCE_PMU) 631 drv_pmu_offs += inc; 632 else 633 drv_grf_offs += inc; 634 635 bank_pins += 8; 636 } 637 638 /* calculate the per-bank recalced_mask */ 639 for (j = 0; j < ctrl->niomux_recalced; j++) { 640 int pin = 0; 641 642 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 643 pin = ctrl->iomux_recalced[j].pin; 644 bank->recalced_mask |= BIT(pin); 645 } 646 } 647 648 /* calculate the per-bank route_mask */ 649 for (j = 0; j < ctrl->niomux_routes; j++) { 650 int pin = 0; 651 652 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 653 pin = ctrl->iomux_routes[j].pin; 654 bank->route_mask |= BIT(pin); 655 } 656 } 657 } 658 659 WARN_ON(nr_pins != ctrl->nr_pins); 660 661 return ctrl; 662 } 663 664 int rockchip_pinctrl_probe(struct udevice *dev) 665 { 666 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 667 struct rockchip_pin_ctrl *ctrl; 668 struct udevice *syscon; 669 struct regmap *regmap; 670 int ret = 0; 671 672 /* get rockchip grf syscon phandle */ 673 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 674 &syscon); 675 if (ret) { 676 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 677 return ret; 678 } 679 680 /* get grf-reg base address */ 681 regmap = syscon_get_regmap(syscon); 682 if (!regmap) { 683 debug("unable to find rockchip grf regmap\n"); 684 return -ENODEV; 685 } 686 priv->regmap_base = regmap; 687 688 /* option: get pmu-reg base address */ 689 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 690 &syscon); 691 if (!ret) { 692 /* get pmugrf-reg base address */ 693 regmap = syscon_get_regmap(syscon); 694 if (!regmap) { 695 debug("unable to find rockchip pmu regmap\n"); 696 return -ENODEV; 697 } 698 priv->regmap_pmu = regmap; 699 } 700 701 ctrl = rockchip_pinctrl_get_soc_data(dev); 702 if (!ctrl) { 703 debug("driver data not available\n"); 704 return -EINVAL; 705 } 706 707 priv->ctrl = ctrl; 708 return 0; 709 } 710