1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/cru_px30.h> 11 #include <asm/arch/grf_px30.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/uart.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cru_px30.h> 16 #include <dt-bindings/clock/px30-cru.h> 17 18 #define PMU_PWRDN_CON 0xff000018 19 #define GRF_CPU_CON1 0xff140504 20 21 #define VIDEO_PHY_BASE 0xff2e0000 22 23 #define SERVICE_CORE_ADDR 0xff508000 24 #define QOS_PRIORITY 0x08 25 26 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 27 28 #ifdef CONFIG_ARM64 29 #include <asm/armv8/mmu.h> 30 31 static struct mm_region px30_mem_map[] = { 32 { 33 .virt = 0x0UL, 34 .phys = 0x0UL, 35 .size = 0xff000000UL, 36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 37 PTE_BLOCK_INNER_SHARE 38 }, { 39 .virt = 0xff000000UL, 40 .phys = 0xff000000UL, 41 .size = 0x01000000UL, 42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 43 PTE_BLOCK_NON_SHARE | 44 PTE_BLOCK_PXN | PTE_BLOCK_UXN 45 }, { 46 /* List terminator */ 47 0, 48 } 49 }; 50 51 struct mm_region *mem_map = px30_mem_map; 52 #endif 53 54 int arch_cpu_init(void) 55 { 56 #ifdef CONFIG_SPL_BUILD 57 /* We do some SoC one time setting here. */ 58 /* Disable the ddr secure region setting to make it non-secure */ 59 #endif 60 /* Enable PD_VO (default disable at reset) */ 61 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 62 63 #ifdef CONFIG_TPL_BUILD 64 /* Set cpu qos priority */ 65 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); 66 #endif 67 68 /* Disable video phy bandgap by default */ 69 writel(0x82, VIDEO_PHY_BASE + 0x0000); 70 writel(0x05, VIDEO_PHY_BASE + 0x03ac); 71 72 /* Clear the force_jtag */ 73 rk_clrreg(GRF_CPU_CON1, 1 << 7); 74 75 return 0; 76 } 77 78 #define GRF_BASE 0xff140000 79 #define UART2_BASE 0xff160000 80 #define CRU_BASE 0xff2b0000 81 void board_debug_uart_init(void) 82 { 83 static struct px30_grf * const grf = (void *)GRF_BASE; 84 85 /* GRF_IOFUNC_CON0 */ 86 enum { 87 CON_IOMUX_UART2SEL_SHIFT = 10, 88 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 89 CON_IOMUX_UART2SEL_M0 = 0, 90 CON_IOMUX_UART2SEL_M1, 91 CON_IOMUX_UART2SEL_USBPHY, 92 }; 93 94 #ifdef CONFIG_TPL_BUILD 95 static struct px30_cru * const cru = (void *)CRU_BASE; 96 static struct rk_uart * const uart = (void *)UART2_BASE; 97 98 /* GRF_GPIO2BH_IOMUX */ 99 enum { 100 GPIO2B7_SHIFT = 12, 101 GPIO2B7_MASK = 0xf << GPIO2B7_SHIFT, 102 GPIO2B7_GPIO = 0, 103 GPIO2B7_CIF_D10M0, 104 GPIO2B7_I2C2_SCL, 105 106 GPIO2B6_SHIFT = 8, 107 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, 108 GPIO2B6_GPIO = 0, 109 GPIO2B6_CIF_D1M0, 110 GPIO2B6_UART2_RXM1, 111 112 GPIO2B5_SHIFT = 4, 113 GPIO2B5_MASK = 0xf << GPIO2B5_SHIFT, 114 GPIO2B5_GPIO = 0, 115 GPIO2B5_PWM2, 116 117 GPIO2B4_SHIFT = 0, 118 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, 119 GPIO2B4_GPIO = 0, 120 GPIO2B4_CIF_D0M0, 121 GPIO2B4_UART2_TXM1, 122 }; 123 124 /* uart_sel_clk default select 24MHz */ 125 rk_clrsetreg(&cru->clksel_con[37], 126 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, 127 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); 128 rk_clrsetreg(&cru->clksel_con[38], 129 UART2_CLK_SEL_MASK, 130 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); 131 132 /* Enable early UART2 */ 133 rk_clrsetreg(&grf->iofunc_con0, 134 CON_IOMUX_UART2SEL_MASK, 135 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); 136 137 /* 138 * Set iomux to UART2_M0 and UART2_M1. 139 * Because uart2_rxm0 and uart2_txm0 are default reset value, 140 * so only need set uart2_rxm1 and uart2_txm1 here. 141 */ 142 rk_clrsetreg(&grf->gpio2bh_iomux, 143 GPIO2B6_MASK, 144 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT); 145 rk_clrsetreg(&grf->gpio2bh_iomux, 146 GPIO2B4_MASK, 147 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); 148 149 /* enable FIFO */ 150 writel(0x1, &uart->sfe); 151 #else 152 #ifdef CONFIG_SPL_BUILD 153 /* GRF_GPIO1DL_IOMUX */ 154 enum { 155 GPIO1D3_SHIFT = 12, 156 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 157 GPIO1D3_GPIO = 0, 158 GPIO1D3_SDMMC_D1, 159 GPIO1D3_UART2_RXM0, 160 161 GPIO1D2_SHIFT = 8, 162 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 163 GPIO1D2_GPIO = 0, 164 GPIO1D2_SDMMC_D0, 165 GPIO1D2_UART2_TXM0, 166 167 GPIO1D1_SHIFT = 4, 168 GPIO1D1_MASK = 0xf << GPIO1D1_SHIFT, 169 GPIO1D1_GPIO = 0, 170 GPIO1D1_SDIO_D3, 171 172 GPIO1D0_SHIFT = 0, 173 GPIO1D0_MASK = 0xf << GPIO1D0_SHIFT, 174 GPIO1D0_GPIO = 0, 175 GPIO1D0_SDIO_D2, 176 }; 177 178 /* Do not set the iomux in U-Boot proper because SD card may using it */ 179 /* Enable early UART2 channel m0 on the px30 */ 180 rk_clrsetreg(&grf->gpio1dl_iomux, 181 GPIO1D3_MASK | GPIO1D2_MASK, 182 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 183 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 184 #endif 185 /* Set channel C as UART2 input */ 186 rk_clrsetreg(&grf->iofunc_con0, 187 CON_IOMUX_UART2SEL_MASK, 188 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 189 #endif 190 } 191 192 int set_armclk_rate(void) 193 { 194 struct px30_clk_priv *priv; 195 struct clk clk; 196 int ret; 197 198 ret = rockchip_get_clk(&clk.dev); 199 if (ret) { 200 printf("Failed to get clk dev\n"); 201 return ret; 202 } 203 clk.id = ARMCLK; 204 priv = dev_get_priv(clk.dev); 205 ret = clk_set_rate(&clk, priv->armclk_hz); 206 if (ret < 0) { 207 printf("Failed to set armclk %lu\n", priv->armclk_hz); 208 return ret; 209 } 210 priv->set_armclk_rate = true; 211 212 return 0; 213 } 214