xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision 5d96bba97e39b7f095cf6cf4e3de9c2d4962f654)
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &sdhci;
10		mmc1 = &sdmmc0;
11		mmc2 = &sdmmc1;
12	};
13
14	chosen {
15		stdout-path = &uart2;
16		u-boot,spl-boot-order = &sdhci, &nandc0, &spi_nand, &spi_nor;
17	};
18};
19
20&crypto {
21	u-boot,dm-pre-reloc;
22};
23
24&uart2 {
25	clock-frequency = <24000000>;
26	u-boot,dm-spl;
27	status = "okay";
28};
29
30&grf {
31	u-boot,dm-pre-reloc;
32	status = "okay";
33};
34
35&pmugrf {
36	u-boot,dm-pre-reloc;
37	status = "okay";
38};
39
40&usb2phy0_grf {
41	u-boot,dm-pre-reloc;
42	status = "okay";
43};
44
45&usbdrd30 {
46	u-boot,dm-pre-reloc;
47	status = "okay";
48};
49
50&usbdrd_dwc3 {
51	u-boot,dm-pre-reloc;
52	status = "okay";
53};
54
55&usbhost30 {
56	u-boot,dm-pre-reloc;
57	status = "okay";
58};
59
60&usbhost_dwc3 {
61	u-boot,dm-pre-reloc;
62	status = "okay";
63};
64
65&usb2phy0 {
66	u-boot,dm-pre-reloc;
67	status = "okay";
68};
69
70&u2phy0_otg {
71	u-boot,dm-pre-reloc;
72	status = "okay";
73};
74
75&u2phy0_host {
76	u-boot,dm-pre-reloc;
77	status = "okay";
78};
79
80&cru {
81	u-boot,dm-pre-reloc;
82	status = "okay";
83};
84
85&pmucru {
86	u-boot,dm-pre-reloc;
87	status = "okay";
88};
89
90&sfc {
91	u-boot,dm-spl;
92	/delete-property/ assigned-clocks;
93	/delete-property/ assigned-clock-rates;
94	status = "okay";
95
96	#address-cells = <1>;
97	#size-cells = <0>;
98	spi_nand: flash@0 {
99		u-boot,dm-spl;
100		compatible = "spi-nand";
101		reg = <0>;
102		spi-tx-bus-width = <1>;
103		spi-rx-bus-width = <4>;
104		spi-max-frequency = <96000000>;
105	};
106
107	spi_nor: flash@1 {
108		u-boot,dm-spl;
109		compatible = "jedec,spi-nor";
110		label = "sfc_nor";
111		reg = <0>;
112		spi-tx-bus-width = <1>;
113		spi-rx-bus-width = <4>;
114		spi-max-frequency = <100000000>;
115	};
116};
117
118&saradc {
119	u-boot,dm-spl;
120	status = "okay";
121};
122
123&sdmmc0 {
124	u-boot,dm-spl;
125	status = "okay";
126};
127
128&sdmmc1 {
129	u-boot,dm-spl;
130	status = "okay";
131};
132
133&sdhci {
134	bus-width = <8>;
135	u-boot,dm-spl;
136	mmc-hs200-1_8v;
137	status = "okay";
138};
139
140&nandc0 {
141	u-boot,dm-spl;
142	status = "okay";
143	#address-cells = <1>;
144	#size-cells = <0>;
145
146	nand@0 {
147		u-boot,dm-spl;
148		reg = <0>;
149		nand-ecc-mode = "hw_syndrome";
150		nand-ecc-strength = <16>;
151		nand-ecc-step-size = <1024>;
152	};
153};
154