/* * (C) Copyright 2020 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ / { aliases { mmc0 = &sdhci; mmc1 = &sdmmc0; mmc2 = &sdmmc1; }; chosen { stdout-path = &uart2; u-boot,spl-boot-order = &sdhci, &nandc0, &spi_nand, &spi_nor; }; }; &crypto { u-boot,dm-pre-reloc; }; &uart2 { clock-frequency = <24000000>; u-boot,dm-spl; status = "okay"; }; &grf { u-boot,dm-pre-reloc; status = "okay"; }; &pmugrf { u-boot,dm-pre-reloc; status = "okay"; }; &usb2phy0_grf { u-boot,dm-pre-reloc; status = "okay"; }; &usbdrd30 { u-boot,dm-pre-reloc; status = "okay"; }; &usbdrd_dwc3 { u-boot,dm-pre-reloc; status = "okay"; }; &usbhost30 { u-boot,dm-pre-reloc; status = "okay"; }; &usbhost_dwc3 { u-boot,dm-pre-reloc; status = "okay"; }; &usb2phy0 { u-boot,dm-pre-reloc; status = "okay"; }; &u2phy0_otg { u-boot,dm-pre-reloc; status = "okay"; }; &u2phy0_host { u-boot,dm-pre-reloc; status = "okay"; }; &cru { u-boot,dm-pre-reloc; status = "okay"; }; &pmucru { u-boot,dm-pre-reloc; status = "okay"; }; &sfc { u-boot,dm-spl; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-rates; status = "okay"; #address-cells = <1>; #size-cells = <0>; spi_nand: flash@0 { u-boot,dm-spl; compatible = "spi-nand"; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <96000000>; }; spi_nor: flash@1 { u-boot,dm-spl; compatible = "jedec,spi-nor"; label = "sfc_nor"; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <100000000>; }; }; &saradc { u-boot,dm-spl; status = "okay"; }; &sdmmc0 { u-boot,dm-spl; status = "okay"; }; &sdmmc1 { u-boot,dm-spl; status = "okay"; }; &sdhci { bus-width = <8>; u-boot,dm-spl; mmc-hs200-1_8v; status = "okay"; }; &nandc0 { u-boot,dm-spl; status = "okay"; #address-cells = <1>; #size-cells = <0>; nand@0 { u-boot,dm-spl; reg = <0>; nand-ecc-mode = "hw_syndrome"; nand-ecc-strength = <16>; nand-ecc-step-size = <1024>; }; };