1be7064f8SJoseph Chen/* 2be7064f8SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3be7064f8SJoseph Chen * 4be7064f8SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5be7064f8SJoseph Chen */ 6be7064f8SJoseph Chen 7be7064f8SJoseph Chen/ { 8be7064f8SJoseph Chen aliases { 9be7064f8SJoseph Chen mmc0 = &sdhci; 10be7064f8SJoseph Chen mmc1 = &sdmmc0; 11be7064f8SJoseph Chen mmc2 = &sdmmc1; 12be7064f8SJoseph Chen }; 13be7064f8SJoseph Chen 14be7064f8SJoseph Chen chosen { 15be7064f8SJoseph Chen stdout-path = &uart2; 16*5d96bba9SYifeng Zhao u-boot,spl-boot-order = &sdhci, &nandc0, &spi_nand, &spi_nor; 17be7064f8SJoseph Chen }; 18be7064f8SJoseph Chen}; 19be7064f8SJoseph Chen 2094d677daSLin Jinhan&crypto { 2194d677daSLin Jinhan u-boot,dm-pre-reloc; 2294d677daSLin Jinhan}; 2394d677daSLin Jinhan 24be7064f8SJoseph Chen&uart2 { 25be7064f8SJoseph Chen clock-frequency = <24000000>; 26e6b32526SJoseph Chen u-boot,dm-spl; 27be7064f8SJoseph Chen status = "okay"; 28be7064f8SJoseph Chen}; 29be7064f8SJoseph Chen 30be7064f8SJoseph Chen&grf { 31be7064f8SJoseph Chen u-boot,dm-pre-reloc; 32be7064f8SJoseph Chen status = "okay"; 33be7064f8SJoseph Chen}; 34be7064f8SJoseph Chen 35be7064f8SJoseph Chen&pmugrf { 36be7064f8SJoseph Chen u-boot,dm-pre-reloc; 37be7064f8SJoseph Chen status = "okay"; 38be7064f8SJoseph Chen}; 39be7064f8SJoseph Chen 40782f7efbSRen Jianing&usb2phy0_grf { 41782f7efbSRen Jianing u-boot,dm-pre-reloc; 42782f7efbSRen Jianing status = "okay"; 43782f7efbSRen Jianing}; 44782f7efbSRen Jianing 45782f7efbSRen Jianing&usbdrd30 { 46782f7efbSRen Jianing u-boot,dm-pre-reloc; 47782f7efbSRen Jianing status = "okay"; 48782f7efbSRen Jianing}; 49782f7efbSRen Jianing 50782f7efbSRen Jianing&usbdrd_dwc3 { 51782f7efbSRen Jianing u-boot,dm-pre-reloc; 52782f7efbSRen Jianing status = "okay"; 53782f7efbSRen Jianing}; 54782f7efbSRen Jianing 55782f7efbSRen Jianing&usbhost30 { 56782f7efbSRen Jianing u-boot,dm-pre-reloc; 57782f7efbSRen Jianing status = "okay"; 58782f7efbSRen Jianing}; 59782f7efbSRen Jianing 60782f7efbSRen Jianing&usbhost_dwc3 { 61782f7efbSRen Jianing u-boot,dm-pre-reloc; 62782f7efbSRen Jianing status = "okay"; 63782f7efbSRen Jianing}; 64782f7efbSRen Jianing 65782f7efbSRen Jianing&usb2phy0 { 66782f7efbSRen Jianing u-boot,dm-pre-reloc; 67782f7efbSRen Jianing status = "okay"; 68782f7efbSRen Jianing}; 69782f7efbSRen Jianing 70782f7efbSRen Jianing&u2phy0_otg { 71782f7efbSRen Jianing u-boot,dm-pre-reloc; 72782f7efbSRen Jianing status = "okay"; 73782f7efbSRen Jianing}; 74782f7efbSRen Jianing 75782f7efbSRen Jianing&u2phy0_host { 76782f7efbSRen Jianing u-boot,dm-pre-reloc; 77782f7efbSRen Jianing status = "okay"; 78782f7efbSRen Jianing}; 79782f7efbSRen Jianing 80be7064f8SJoseph Chen&cru { 81be7064f8SJoseph Chen u-boot,dm-pre-reloc; 82be7064f8SJoseph Chen status = "okay"; 83be7064f8SJoseph Chen}; 84be7064f8SJoseph Chen 85be7064f8SJoseph Chen&pmucru { 86be7064f8SJoseph Chen u-boot,dm-pre-reloc; 87be7064f8SJoseph Chen status = "okay"; 88be7064f8SJoseph Chen}; 89be7064f8SJoseph Chen 90b50fa296SJon Lin&sfc { 91b50fa296SJon Lin u-boot,dm-spl; 92b50fa296SJon Lin /delete-property/ assigned-clocks; 93b50fa296SJon Lin /delete-property/ assigned-clock-rates; 94b50fa296SJon Lin status = "okay"; 95b50fa296SJon Lin 96b50fa296SJon Lin #address-cells = <1>; 97b50fa296SJon Lin #size-cells = <0>; 98b50fa296SJon Lin spi_nand: flash@0 { 99b50fa296SJon Lin u-boot,dm-spl; 100b50fa296SJon Lin compatible = "spi-nand"; 101b50fa296SJon Lin reg = <0>; 102b50fa296SJon Lin spi-tx-bus-width = <1>; 103b50fa296SJon Lin spi-rx-bus-width = <4>; 104b50fa296SJon Lin spi-max-frequency = <96000000>; 105b50fa296SJon Lin }; 106b50fa296SJon Lin 107b50fa296SJon Lin spi_nor: flash@1 { 108b50fa296SJon Lin u-boot,dm-spl; 109b50fa296SJon Lin compatible = "jedec,spi-nor"; 110b50fa296SJon Lin label = "sfc_nor"; 111b50fa296SJon Lin reg = <0>; 112b50fa296SJon Lin spi-tx-bus-width = <1>; 113b50fa296SJon Lin spi-rx-bus-width = <4>; 114b50fa296SJon Lin spi-max-frequency = <100000000>; 115b50fa296SJon Lin }; 116b50fa296SJon Lin}; 117b50fa296SJon Lin 118be7064f8SJoseph Chen&saradc { 119be7064f8SJoseph Chen u-boot,dm-spl; 120be7064f8SJoseph Chen status = "okay"; 121be7064f8SJoseph Chen}; 122be7064f8SJoseph Chen 123be7064f8SJoseph Chen&sdmmc0 { 124e6b32526SJoseph Chen u-boot,dm-spl; 125be7064f8SJoseph Chen status = "okay"; 126be7064f8SJoseph Chen}; 127be7064f8SJoseph Chen 128be7064f8SJoseph Chen&sdmmc1 { 129e6b32526SJoseph Chen u-boot,dm-spl; 130be7064f8SJoseph Chen status = "okay"; 131be7064f8SJoseph Chen}; 132be7064f8SJoseph Chen 133be7064f8SJoseph Chen&sdhci { 134b48cb5c2SJason Zhu bus-width = <8>; 135e6b32526SJoseph Chen u-boot,dm-spl; 136311b34e2SYifeng Zhao mmc-hs200-1_8v; 137be7064f8SJoseph Chen status = "okay"; 138be7064f8SJoseph Chen}; 139be7064f8SJoseph Chen 140*5d96bba9SYifeng Zhao&nandc0 { 141*5d96bba9SYifeng Zhao u-boot,dm-spl; 142*5d96bba9SYifeng Zhao status = "okay"; 143*5d96bba9SYifeng Zhao #address-cells = <1>; 144*5d96bba9SYifeng Zhao #size-cells = <0>; 145*5d96bba9SYifeng Zhao 146*5d96bba9SYifeng Zhao nand@0 { 147*5d96bba9SYifeng Zhao u-boot,dm-spl; 148*5d96bba9SYifeng Zhao reg = <0>; 149*5d96bba9SYifeng Zhao nand-ecc-mode = "hw_syndrome"; 150*5d96bba9SYifeng Zhao nand-ecc-strength = <16>; 151*5d96bba9SYifeng Zhao nand-ecc-step-size = <1024>; 152*5d96bba9SYifeng Zhao }; 153*5d96bba9SYifeng Zhao}; 154