1# 2# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14ENABLE_PIE := 1 15PROGRAMMABLE_RESET_ADDRESS := 1 16BL2_IN_XIP_MEM := 1 17 18# Default Device tree 19DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 20 21STM32MP25 := 1 22 23# STM32 image header version v2.2 24STM32_HEADER_VERSION_MAJOR := 2 25STM32_HEADER_VERSION_MINOR := 2 26 27# Set load address for serial boot devices 28DWL_BUFFER_BASE ?= 0x87000000 29 30# DDR types 31STM32MP_DDR3_TYPE ?= 0 32STM32MP_DDR4_TYPE ?= 0 33STM32MP_LPDDR4_TYPE ?= 0 34ifeq (${STM32MP_DDR3_TYPE},1) 35DDR_TYPE := ddr3 36endif 37ifeq (${STM32MP_DDR4_TYPE},1) 38DDR_TYPE := ddr4 39endif 40ifeq (${STM32MP_LPDDR4_TYPE},1) 41DDR_TYPE := lpddr4 42endif 43 44# DDR features 45STM32MP_DDR_DUAL_AXI_PORT := 1 46STM32MP_DDR_FIP_IO_STORAGE := 1 47 48# Device tree 49BL2_DTSI := stm32mp25-bl2.dtsi 50FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 51BL31_DTSI := stm32mp25-bl31.dtsi 52FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 53 54# Macros and rules to build TF binary 55STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 56STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 57STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 58 59STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 60STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 61STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 62ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 63STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 64STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 65STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 66endif 67FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 68# Add the FW_CONFIG to FIP and specify the same to certtool 69$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 70# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 71$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config)) 72ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 73# Add the FW_DDR to FIP and specify the same to certtool 74$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 75endif 76 77# Enable flags for C files 78$(eval $(call assert_booleans,\ 79 $(sort \ 80 STM32MP_DDR_DUAL_AXI_PORT \ 81 STM32MP_DDR_FIP_IO_STORAGE \ 82 STM32MP_DDR3_TYPE \ 83 STM32MP_DDR4_TYPE \ 84 STM32MP_LPDDR4_TYPE \ 85 STM32MP25 \ 86))) 87 88$(eval $(call assert_numerics,\ 89 $(sort \ 90 PLAT_PARTITION_MAX_ENTRIES \ 91 STM32_HEADER_VERSION_MAJOR \ 92 STM32_TF_A_COPIES \ 93))) 94 95$(eval $(call add_defines,\ 96 $(sort \ 97 DWL_BUFFER_BASE \ 98 PLAT_DEF_FIP_UUID \ 99 PLAT_PARTITION_MAX_ENTRIES \ 100 PLAT_TBBR_IMG_DEF \ 101 STM32_TF_A_COPIES \ 102 STM32MP_DDR_DUAL_AXI_PORT \ 103 STM32MP_DDR_FIP_IO_STORAGE \ 104 STM32MP_DDR3_TYPE \ 105 STM32MP_DDR4_TYPE \ 106 STM32MP_LPDDR4_TYPE \ 107 STM32MP25 \ 108))) 109 110# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 111# Disable mbranch-protection to avoid adding useless code 112TF_CFLAGS += -mbranch-protection=none 113 114# Include paths and source files 115PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 116PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 117PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 118 119PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 120PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 121PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 122 123PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 124 drivers/st/pmic/stpmic2.c \ 125 126PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 127 128PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 129 130PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 131 drivers/st/reset/stm32mp2_reset.c \ 132 plat/st/stm32mp2/stm32mp2_syscfg.c 133 134PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 135 drivers/st/clk/clk-stm32mp2.c 136 137BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 138 139BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 140 plat/st/stm32mp2/plat_ddr.c 141 142ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 143BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 144endif 145 146ifeq (${STM32MP_USB_PROGRAMMER},1) 147BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 148endif 149 150BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 151 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 152 drivers/st/ddr/stm32mp2_ram.c 153 154BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 155 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 156 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 157 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 158 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 159 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 160 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 161 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 162 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 163 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 164 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 165 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 166 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 167 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 168 169BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 170 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 171 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 172 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 173 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 174 175# BL31 sources 176BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 177 178BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 179 plat/st/stm32mp2/stm32mp2_pm.c \ 180 plat/st/stm32mp2/stm32mp2_topology.c 181# Generic GIC v2 182include drivers/arm/gic/v2/gicv2.mk 183 184BL31_SOURCES += ${GICV2_SOURCES} \ 185 plat/common/plat_gicv2.c \ 186 plat/st/common/stm32mp_gic.c 187 188# Generic PSCI 189BL31_SOURCES += plat/common/plat_psci_common.c 190 191# Compilation rules 192.PHONY: check_ddr_type 193.SUFFIXES: 194 195bl2: check_ddr_type 196 197check_ddr_type: 198 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 199 $(STM32MP_DDR4_TYPE) + \ 200 $(STM32MP_LPDDR4_TYPE))))) 201 @if [ ${DDR_TYPE} != 1 ]; then \ 202 echo "One and only one DDR type must be defined"; \ 203 false; \ 204 fi 205 206# Create DTB file for BL31 207${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 208 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 209 @echo '#include "${BL31_DTSI}"' >> $@ 210 211${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts 212 213include plat/st/common/common_rules.mk 214