135527fb4SYann Gautier# 2197ac780SYann Gautier# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 335527fb4SYann Gautier# 435527fb4SYann Gautier# SPDX-License-Identifier: BSD-3-Clause 535527fb4SYann Gautier# 635527fb4SYann Gautier 766b4c5c5SYann Gautier# Extra partitions used to find FIP, contains: 866b4c5c5SYann Gautier# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 966b4c5c5SYann GautierSTM32_EXTRA_PARTS := 6 1066b4c5c5SYann Gautier 1135527fb4SYann Gautierinclude plat/st/common/common.mk 1235527fb4SYann Gautier 1335527fb4SYann GautierCRASH_REPORTING := 1 1435527fb4SYann GautierENABLE_PIE := 1 1535527fb4SYann GautierPROGRAMMABLE_RESET_ADDRESS := 1 16db77f8bfSYann GautierBL2_IN_XIP_MEM := 1 1735527fb4SYann Gautier 1835527fb4SYann Gautier# Default Device tree 1935527fb4SYann GautierDTB_FILE_NAME ?= stm32mp257f-ev1.dtb 2035527fb4SYann Gautier 2135527fb4SYann GautierSTM32MP25 := 1 2235527fb4SYann Gautier 2335527fb4SYann Gautier# STM32 image header version v2.2 2435527fb4SYann GautierSTM32_HEADER_VERSION_MAJOR := 2 2535527fb4SYann GautierSTM32_HEADER_VERSION_MINOR := 2 2635527fb4SYann Gautier 272e905c06SYann Gautier# Set load address for serial boot devices 282e905c06SYann GautierDWL_BUFFER_BASE ?= 0x87000000 292e905c06SYann Gautier 30d07e9467SNicolas Le Bayon# DDR types 31d07e9467SNicolas Le BayonSTM32MP_DDR3_TYPE ?= 0 32d07e9467SNicolas Le BayonSTM32MP_DDR4_TYPE ?= 0 33d07e9467SNicolas Le BayonSTM32MP_LPDDR4_TYPE ?= 0 34d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR3_TYPE},1) 35d07e9467SNicolas Le BayonDDR_TYPE := ddr3 36d07e9467SNicolas Le Bayonendif 37d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR4_TYPE},1) 38d07e9467SNicolas Le BayonDDR_TYPE := ddr4 39d07e9467SNicolas Le Bayonendif 40d07e9467SNicolas Le Bayonifeq (${STM32MP_LPDDR4_TYPE},1) 41d07e9467SNicolas Le BayonDDR_TYPE := lpddr4 42d07e9467SNicolas Le Bayonendif 43d07e9467SNicolas Le Bayon 44ae84525fSMaxime Méré# DDR features 45ae84525fSMaxime MéréSTM32MP_DDR_FIP_IO_STORAGE := 1 46ae84525fSMaxime Méré 47e5839ed7SYann Gautier# Device tree 48e5839ed7SYann GautierBL2_DTSI := stm32mp25-bl2.dtsi 49e5839ed7SYann GautierFDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 50e5839ed7SYann Gautier 51e5839ed7SYann Gautier# Macros and rules to build TF binary 52e5839ed7SYann GautierSTM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 53e5839ed7SYann GautierSTM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 54e5839ed7SYann GautierSTM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 55e5839ed7SYann Gautier 565af9369cSYann GautierSTM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 575af9369cSYann GautierSTM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 58ae84525fSMaxime Méréifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 59ae84525fSMaxime MéréSTM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 60ae84525fSMaxime MéréSTM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 61ae84525fSMaxime MéréSTM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 62ae84525fSMaxime Méréendif 635af9369cSYann GautierFDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 645af9369cSYann Gautier# Add the FW_CONFIG to FIP and specify the same to certtool 655af9369cSYann Gautier$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 66ae84525fSMaxime Méréifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 67ae84525fSMaxime Méré# Add the FW_DDR to FIP and specify the same to certtool 68ae84525fSMaxime Méré$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 69ae84525fSMaxime Méréendif 705af9369cSYann Gautier 71db77f8bfSYann Gautier# Enable flags for C files 72db77f8bfSYann Gautier$(eval $(call assert_booleans,\ 73db77f8bfSYann Gautier $(sort \ 74ae84525fSMaxime Méré STM32MP_DDR_FIP_IO_STORAGE \ 75d07e9467SNicolas Le Bayon STM32MP_DDR3_TYPE \ 76d07e9467SNicolas Le Bayon STM32MP_DDR4_TYPE \ 77d07e9467SNicolas Le Bayon STM32MP_LPDDR4_TYPE \ 78db77f8bfSYann Gautier STM32MP25 \ 79db77f8bfSYann Gautier))) 80db77f8bfSYann Gautier 81db77f8bfSYann Gautier$(eval $(call assert_numerics,\ 82db77f8bfSYann Gautier $(sort \ 83db77f8bfSYann Gautier PLAT_PARTITION_MAX_ENTRIES \ 84db77f8bfSYann Gautier STM32_HEADER_VERSION_MAJOR \ 85db77f8bfSYann Gautier STM32_TF_A_COPIES \ 86db77f8bfSYann Gautier))) 87db77f8bfSYann Gautier 882e905c06SYann Gautier$(eval $(call add_defines,\ 892e905c06SYann Gautier $(sort \ 902e905c06SYann Gautier DWL_BUFFER_BASE \ 91ae84525fSMaxime Méré PLAT_DEF_FIP_UUID \ 92db77f8bfSYann Gautier PLAT_PARTITION_MAX_ENTRIES \ 93db77f8bfSYann Gautier PLAT_TBBR_IMG_DEF \ 94db77f8bfSYann Gautier STM32_TF_A_COPIES \ 95ae84525fSMaxime Méré STM32MP_DDR_FIP_IO_STORAGE \ 96d07e9467SNicolas Le Bayon STM32MP_DDR3_TYPE \ 97d07e9467SNicolas Le Bayon STM32MP_DDR4_TYPE \ 98d07e9467SNicolas Le Bayon STM32MP_LPDDR4_TYPE \ 99db77f8bfSYann Gautier STM32MP25 \ 1002e905c06SYann Gautier))) 1012e905c06SYann Gautier 10235527fb4SYann Gautier# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 10335527fb4SYann Gautier# Disable mbranch-protection to avoid adding useless code 10435527fb4SYann GautierTF_CFLAGS += -mbranch-protection=none 10535527fb4SYann Gautier 10635527fb4SYann Gautier# Include paths and source files 10735527fb4SYann GautierPLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 10835527fb4SYann Gautier 10935527fb4SYann GautierPLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 11087a940e0SYann GautierPLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 11135527fb4SYann GautierPLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 11235527fb4SYann Gautier 113817f42f0SPascal PailletPLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 114817f42f0SPascal Paillet drivers/st/pmic/stpmic2.c \ 115817f42f0SPascal Paillet 116817f42f0SPascal PailletPLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 117817f42f0SPascal Paillet 118db77f8bfSYann GautierPLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 119db77f8bfSYann Gautier 120f829d7dfSGabriel FernandezPLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 121154e6e62SYann Gautier drivers/st/reset/stm32mp2_reset.c \ 122154e6e62SYann Gautier plat/st/stm32mp2/stm32mp2_syscfg.c 123197ac780SYann Gautier 124615f31feSGabriel FernandezPLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 125615f31feSGabriel Fernandez drivers/st/clk/clk-stm32mp2.c 126615f31feSGabriel Fernandez 12735527fb4SYann GautierBL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 128db77f8bfSYann Gautier 129*e2d6e5e2SPascal PailletBL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 130*e2d6e5e2SPascal Paillet plat/st/stm32mp2/plat_ddr.c 13135527fb4SYann Gautier 132db77f8bfSYann Gautierifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 133db77f8bfSYann GautierBL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 134db77f8bfSYann Gautierendif 135db77f8bfSYann Gautier 1362e905c06SYann Gautierifeq (${STM32MP_USB_PROGRAMMER},1) 1372e905c06SYann GautierBL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 1382e905c06SYann Gautierendif 1392e905c06SYann Gautier 1405e0be8c0SYann GautierBL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c 1415e0be8c0SYann Gautier 14203020b66SYann Gautier# BL31 sources 14303020b66SYann GautierBL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 14403020b66SYann Gautier 14503020b66SYann GautierBL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 14603020b66SYann Gautier plat/st/stm32mp2/stm32mp2_pm.c \ 14703020b66SYann Gautier plat/st/stm32mp2/stm32mp2_topology.c 14803020b66SYann Gautier# Generic GIC v2 14903020b66SYann Gautierinclude drivers/arm/gic/v2/gicv2.mk 15003020b66SYann Gautier 15103020b66SYann GautierBL31_SOURCES += ${GICV2_SOURCES} \ 15203020b66SYann Gautier plat/common/plat_gicv2.c \ 15303020b66SYann Gautier plat/st/common/stm32mp_gic.c 15403020b66SYann Gautier 15503020b66SYann Gautier# Generic PSCI 15603020b66SYann GautierBL31_SOURCES += plat/common/plat_psci_common.c 15703020b66SYann Gautier 158db77f8bfSYann Gautier# Compilation rules 159d07e9467SNicolas Le Bayon.PHONY: check_ddr_type 160d07e9467SNicolas Le Bayon.SUFFIXES: 161d07e9467SNicolas Le Bayon 162d07e9467SNicolas Le Bayonbl2: check_ddr_type 163d07e9467SNicolas Le Bayon 164d07e9467SNicolas Le Bayoncheck_ddr_type: 165d07e9467SNicolas Le Bayon $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 166d07e9467SNicolas Le Bayon $(STM32MP_DDR4_TYPE) + \ 167d07e9467SNicolas Le Bayon $(STM32MP_LPDDR4_TYPE))))) 168d07e9467SNicolas Le Bayon @if [ ${DDR_TYPE} != 1 ]; then \ 169d07e9467SNicolas Le Bayon echo "One and only one DDR type must be defined"; \ 170d07e9467SNicolas Le Bayon false; \ 171d07e9467SNicolas Le Bayon fi 172d07e9467SNicolas Le Bayon 17335527fb4SYann Gautierinclude plat/st/common/common_rules.mk 174