135527fb4SYann Gautier# 2197ac780SYann Gautier# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 335527fb4SYann Gautier# 435527fb4SYann Gautier# SPDX-License-Identifier: BSD-3-Clause 535527fb4SYann Gautier# 635527fb4SYann Gautier 766b4c5c5SYann Gautier# Extra partitions used to find FIP, contains: 866b4c5c5SYann Gautier# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 966b4c5c5SYann GautierSTM32_EXTRA_PARTS := 6 1066b4c5c5SYann Gautier 1135527fb4SYann Gautierinclude plat/st/common/common.mk 1235527fb4SYann Gautier 1335527fb4SYann GautierCRASH_REPORTING := 1 1435527fb4SYann GautierENABLE_PIE := 1 1535527fb4SYann GautierPROGRAMMABLE_RESET_ADDRESS := 1 16db77f8bfSYann GautierBL2_IN_XIP_MEM := 1 1735527fb4SYann Gautier 1835527fb4SYann Gautier# Default Device tree 1935527fb4SYann GautierDTB_FILE_NAME ?= stm32mp257f-ev1.dtb 2035527fb4SYann Gautier 2135527fb4SYann GautierSTM32MP25 := 1 2235527fb4SYann Gautier 2335527fb4SYann Gautier# STM32 image header version v2.2 2435527fb4SYann GautierSTM32_HEADER_VERSION_MAJOR := 2 2535527fb4SYann GautierSTM32_HEADER_VERSION_MINOR := 2 2635527fb4SYann Gautier 272e905c06SYann Gautier# Set load address for serial boot devices 282e905c06SYann GautierDWL_BUFFER_BASE ?= 0x87000000 292e905c06SYann Gautier 30*d07e9467SNicolas Le Bayon# DDR types 31*d07e9467SNicolas Le BayonSTM32MP_DDR3_TYPE ?= 0 32*d07e9467SNicolas Le BayonSTM32MP_DDR4_TYPE ?= 0 33*d07e9467SNicolas Le BayonSTM32MP_LPDDR4_TYPE ?= 0 34*d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR3_TYPE},1) 35*d07e9467SNicolas Le BayonDDR_TYPE := ddr3 36*d07e9467SNicolas Le Bayonendif 37*d07e9467SNicolas Le Bayonifeq (${STM32MP_DDR4_TYPE},1) 38*d07e9467SNicolas Le BayonDDR_TYPE := ddr4 39*d07e9467SNicolas Le Bayonendif 40*d07e9467SNicolas Le Bayonifeq (${STM32MP_LPDDR4_TYPE},1) 41*d07e9467SNicolas Le BayonDDR_TYPE := lpddr4 42*d07e9467SNicolas Le Bayonendif 43*d07e9467SNicolas Le Bayon 44e5839ed7SYann Gautier# Device tree 45e5839ed7SYann GautierBL2_DTSI := stm32mp25-bl2.dtsi 46e5839ed7SYann GautierFDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 47e5839ed7SYann Gautier 48e5839ed7SYann Gautier# Macros and rules to build TF binary 49e5839ed7SYann GautierSTM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 50e5839ed7SYann GautierSTM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 51e5839ed7SYann GautierSTM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 52e5839ed7SYann Gautier 535af9369cSYann GautierSTM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 545af9369cSYann GautierSTM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 555af9369cSYann GautierFDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 565af9369cSYann Gautier# Add the FW_CONFIG to FIP and specify the same to certtool 575af9369cSYann Gautier$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 585af9369cSYann Gautier 59db77f8bfSYann Gautier# Enable flags for C files 60db77f8bfSYann Gautier$(eval $(call assert_booleans,\ 61db77f8bfSYann Gautier $(sort \ 62*d07e9467SNicolas Le Bayon STM32MP_DDR3_TYPE \ 63*d07e9467SNicolas Le Bayon STM32MP_DDR4_TYPE \ 64*d07e9467SNicolas Le Bayon STM32MP_LPDDR4_TYPE \ 65db77f8bfSYann Gautier STM32MP25 \ 66db77f8bfSYann Gautier))) 67db77f8bfSYann Gautier 68db77f8bfSYann Gautier$(eval $(call assert_numerics,\ 69db77f8bfSYann Gautier $(sort \ 70db77f8bfSYann Gautier PLAT_PARTITION_MAX_ENTRIES \ 71db77f8bfSYann Gautier STM32_HEADER_VERSION_MAJOR \ 72db77f8bfSYann Gautier STM32_TF_A_COPIES \ 73db77f8bfSYann Gautier))) 74db77f8bfSYann Gautier 752e905c06SYann Gautier$(eval $(call add_defines,\ 762e905c06SYann Gautier $(sort \ 772e905c06SYann Gautier DWL_BUFFER_BASE \ 78db77f8bfSYann Gautier PLAT_PARTITION_MAX_ENTRIES \ 79db77f8bfSYann Gautier PLAT_TBBR_IMG_DEF \ 80db77f8bfSYann Gautier STM32_TF_A_COPIES \ 81*d07e9467SNicolas Le Bayon STM32MP_DDR3_TYPE \ 82*d07e9467SNicolas Le Bayon STM32MP_DDR4_TYPE \ 83*d07e9467SNicolas Le Bayon STM32MP_LPDDR4_TYPE \ 84db77f8bfSYann Gautier STM32MP25 \ 852e905c06SYann Gautier))) 862e905c06SYann Gautier 8735527fb4SYann Gautier# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 8835527fb4SYann Gautier# Disable mbranch-protection to avoid adding useless code 8935527fb4SYann GautierTF_CFLAGS += -mbranch-protection=none 9035527fb4SYann Gautier 9135527fb4SYann Gautier# Include paths and source files 9235527fb4SYann GautierPLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 9335527fb4SYann Gautier 9435527fb4SYann GautierPLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 9587a940e0SYann GautierPLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 9635527fb4SYann GautierPLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 9735527fb4SYann Gautier 98db77f8bfSYann GautierPLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 99db77f8bfSYann Gautier 100f829d7dfSGabriel FernandezPLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 101154e6e62SYann Gautier drivers/st/reset/stm32mp2_reset.c \ 102154e6e62SYann Gautier plat/st/stm32mp2/stm32mp2_syscfg.c 103197ac780SYann Gautier 104615f31feSGabriel FernandezPLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 105615f31feSGabriel Fernandez drivers/st/clk/clk-stm32mp2.c 106615f31feSGabriel Fernandez 10735527fb4SYann GautierBL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 108db77f8bfSYann Gautier 10935527fb4SYann GautierBL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c 11035527fb4SYann Gautier 111db77f8bfSYann Gautierifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 112db77f8bfSYann GautierBL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 113db77f8bfSYann Gautierendif 114db77f8bfSYann Gautier 1152e905c06SYann Gautierifeq (${STM32MP_USB_PROGRAMMER},1) 1162e905c06SYann GautierBL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 1172e905c06SYann Gautierendif 1182e905c06SYann Gautier 1195e0be8c0SYann GautierBL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c 1205e0be8c0SYann Gautier 12103020b66SYann Gautier# BL31 sources 12203020b66SYann GautierBL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 12303020b66SYann Gautier 12403020b66SYann GautierBL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 12503020b66SYann Gautier plat/st/stm32mp2/stm32mp2_pm.c \ 12603020b66SYann Gautier plat/st/stm32mp2/stm32mp2_topology.c 12703020b66SYann Gautier# Generic GIC v2 12803020b66SYann Gautierinclude drivers/arm/gic/v2/gicv2.mk 12903020b66SYann Gautier 13003020b66SYann GautierBL31_SOURCES += ${GICV2_SOURCES} \ 13103020b66SYann Gautier plat/common/plat_gicv2.c \ 13203020b66SYann Gautier plat/st/common/stm32mp_gic.c 13303020b66SYann Gautier 13403020b66SYann Gautier# Generic PSCI 13503020b66SYann GautierBL31_SOURCES += plat/common/plat_psci_common.c 13603020b66SYann Gautier 137db77f8bfSYann Gautier# Compilation rules 138*d07e9467SNicolas Le Bayon.PHONY: check_ddr_type 139*d07e9467SNicolas Le Bayon.SUFFIXES: 140*d07e9467SNicolas Le Bayon 141*d07e9467SNicolas Le Bayonbl2: check_ddr_type 142*d07e9467SNicolas Le Bayon 143*d07e9467SNicolas Le Bayoncheck_ddr_type: 144*d07e9467SNicolas Le Bayon $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 145*d07e9467SNicolas Le Bayon $(STM32MP_DDR4_TYPE) + \ 146*d07e9467SNicolas Le Bayon $(STM32MP_LPDDR4_TYPE))))) 147*d07e9467SNicolas Le Bayon @if [ ${DDR_TYPE} != 1 ]; then \ 148*d07e9467SNicolas Le Bayon echo "One and only one DDR type must be defined"; \ 149*d07e9467SNicolas Le Bayon false; \ 150*d07e9467SNicolas Le Bayon fi 151*d07e9467SNicolas Le Bayon 15235527fb4SYann Gautierinclude plat/st/common/common_rules.mk 153