1 /*
2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/bl_common.h>
10 #include <drivers/arm/pl061_gpio.h>
11 #include <lib/gpt_rme/gpt_rme.h>
12 #if TRANSFER_LIST
13 #include <transfer_list.h>
14 #endif
15 #include <plat/common/platform.h>
16 #if ENABLE_RME
17 #ifdef PLAT_qemu
18 #include <qemu_pas_def.h>
19 #elif PLAT_qemu_sbsa
20 #include <qemu_sbsa_pas_def.h>
21 #endif /* PLAT_qemu */
22 #endif /* ENABLE_RME */
23 #ifdef PLAT_qemu_sbsa
24 #include <sbsa_platform.h>
25 #endif
26
27 #include "qemu_private.h"
28
29 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \
30 BL31_BASE, \
31 BL31_END - BL31_BASE, \
32 MT_MEMORY | MT_RW | EL3_PAS)
33 #define MAP_BL31_RO MAP_REGION_FLAT( \
34 BL_CODE_BASE, \
35 BL_CODE_END - BL_CODE_BASE, \
36 MT_CODE | EL3_PAS), \
37 MAP_REGION_FLAT( \
38 BL_RO_DATA_BASE, \
39 BL_RO_DATA_END \
40 - BL_RO_DATA_BASE, \
41 MT_RO_DATA | EL3_PAS)
42
43 #if USE_COHERENT_MEM
44 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
45 BL_COHERENT_RAM_BASE, \
46 BL_COHERENT_RAM_END \
47 - BL_COHERENT_RAM_BASE, \
48 MT_DEVICE | MT_RW | EL3_PAS)
49 #endif
50
51 #if ENABLE_RME
52 #if (RME_GPT_BITLOCK_BLOCK == 0)
53 #define BITLOCK_BASE UL(0)
54 #define BITLOCK_SIZE UL(0)
55 #else
56
57 /*
58 * Number of bitlock_t entries in the gpt_bitlock array for this platform's
59 * Protected Physical Size. One 8-bit bitlock_t entry covers
60 * 8 * RME_GPT_BITLOCK_BLOCK * 512MB.
61 */
62 #if (PLAT_QEMU_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)))
63 #define BITLOCKS_NUM (PLAT_QEMU_PPS / \
64 (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)))
65 #else
66 #define BITLOCKS_NUM 1
67 #endif
68
69 static bitlock_t gpt_bitlock[BITLOCKS_NUM];
70 #define BITLOCK_BASE (uintptr_t)gpt_bitlock
71 #define BITLOCK_SIZE sizeof(gpt_bitlock)
72 #endif /* RME_GPT_BITLOCK_BLOCK */
73 #endif /* ENABLE_RME */
74
75 /*
76 * Placeholder variables for copying the arguments that have been passed to
77 * BL3-1 from BL2.
78 */
79 static entry_point_info_t bl32_image_ep_info;
80 static entry_point_info_t bl33_image_ep_info;
81 #if ENABLE_RME
82 static entry_point_info_t rmm_image_ep_info;
83 #endif
84 static struct transfer_list_header __maybe_unused *bl31_tl;
85
86 /*******************************************************************************
87 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
88 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
89 * they are lost (potentially). This needs to be done before the MMU is
90 * initialized so that the memory layout can be used while creating page
91 * tables. BL2 has flushed this information to memory, so we are guaranteed
92 * to pick up good data.
93 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)94 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
95 u_register_t arg2, u_register_t arg3)
96 {
97 bool __maybe_unused is64 = false;
98 uint64_t __maybe_unused hval;
99
100 /* Initialize the console to provide early debug support */
101 qemu_console_init();
102
103 /* Platform names have to be lowercase. */
104 #ifdef PLAT_qemu_sbsa
105 sbsa_platform_init();
106 #endif
107
108 /*
109 * Check params passed from BL2
110 */
111 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
112
113 assert(params_from_bl2);
114 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
115 assert(params_from_bl2->h.version >= VERSION_2);
116
117 bl_params_node_t *bl_params = params_from_bl2->head;
118
119 /*
120 * Copy BL33, BL32 and RMM (if present), entry point information.
121 * They are stored in Secure RAM, in BL2's address space.
122 */
123 while (bl_params) {
124 #if defined(__aarch64__) && TRANSFER_LIST
125 if (bl_params->image_id == BL31_IMAGE_ID &&
126 GET_RW(bl_params->ep_info->spsr) == MODE_RW_64)
127 is64 = true;
128 #endif /* defined(__aarch64__) && TRANSFER_LIST */
129 if (bl_params->image_id == BL32_IMAGE_ID)
130 bl32_image_ep_info = *bl_params->ep_info;
131
132 #if ENABLE_RME
133 if (bl_params->image_id == RMM_IMAGE_ID)
134 rmm_image_ep_info = *bl_params->ep_info;
135 #endif
136
137 if (bl_params->image_id == BL33_IMAGE_ID)
138 bl33_image_ep_info = *bl_params->ep_info;
139
140 bl_params = bl_params->next_params_info;
141 }
142
143 if (!bl33_image_ep_info.pc)
144 panic();
145 #if ENABLE_RME
146 if (!rmm_image_ep_info.pc)
147 panic();
148 #endif
149
150 #if TRANSFER_LIST
151 if (!transfer_list_check_header((void *)arg3))
152 return;
153
154 if (is64)
155 hval = TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
156 else
157 hval = TRANSFER_LIST_HANDOFF_R1_VALUE(REGISTER_CONVENTION_VERSION);
158
159 if (arg1 != hval)
160 return;
161 #endif
162
163 bl31_tl = (void *)arg3; /* saved TL address from BL2 */
164 }
165
166 #if ENABLE_RME
167 #if PLAT_qemu
168 /*
169 * The GPT library might modify the gpt regions structure to optimize
170 * the layout, so the array cannot be constant.
171 */
172 static pas_region_t pas_regions[] = {
173 QEMU_PAS_ROOT,
174 QEMU_PAS_SECURE,
175 QEMU_PAS_GPTS,
176 QEMU_PAS_NS0,
177 QEMU_PAS_REALM,
178 QEMU_PAS_NS1,
179 };
180
bl31_adjust_pas_regions(void)181 static inline void bl31_adjust_pas_regions(void) {}
182 #elif PLAT_qemu_sbsa
183 /*
184 * The GPT library might modify the gpt regions structure to optimize
185 * the layout, so the array cannot be constant.
186 */
187 static pas_region_t pas_regions[] = {
188 QEMU_PAS_ROOT,
189 QEMU_PAS_SECURE,
190 QEMU_PAS_GPTS,
191 QEMU_PAS_REALM,
192 QEMU_PAS_NS0,
193 };
194
bl31_adjust_pas_regions(void)195 static void bl31_adjust_pas_regions(void)
196 {
197 uint64_t base_addr = 0, total_size = 0;
198 struct platform_memory_data data;
199 uint32_t node;
200
201 /*
202 * The amount of memory supported by the SBSA platform is dynamic
203 * and dependent on user input. Since the configuration of the GPT
204 * needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
205 * based on the information found in the device tree.
206 */
207
208 for (node = 0; node < sbsa_platform_num_memnodes(); node++) {
209 data = sbsa_platform_memory_node(node);
210
211 if (data.nodeid == 0) {
212 base_addr = data.addr_base;
213 }
214
215 total_size += data.addr_size;
216 }
217
218 /* Index '4' correspond to QEMU_PAS_NS0, see pas_regions[] above */
219 pas_regions[4].base_pa = base_addr;
220 pas_regions[4].size = total_size;
221 }
222 #endif /* PLAT_qemu */
223
bl31_plat_gpt_setup(void)224 static void bl31_plat_gpt_setup(void)
225 {
226 /*
227 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry
228 * covering 1GB (currently the only supported option), then covering
229 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the
230 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
231 */
232 if (gpt_init_l0_tables(PLAT_QEMU_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE,
233 PLAT_QEMU_L0_GPT_SIZE) < 0) {
234 ERROR("gpt_init_l0_tables() failed!\n");
235 panic();
236 }
237
238 bl31_adjust_pas_regions();
239
240 /* Carve out defined PAS ranges. */
241 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
242 PLAT_QEMU_L1_GPT_BASE,
243 PLAT_QEMU_L1_GPT_SIZE,
244 pas_regions,
245 (unsigned int)(sizeof(pas_regions) /
246 sizeof(pas_region_t))) < 0) {
247 ERROR("gpt_init_pas_l1_tables() failed!\n");
248 panic();
249 }
250
251 INFO("Enabling Granule Protection Checks\n");
252 if (gpt_enable() < 0) {
253 ERROR("gpt_enable() failed!\n");
254 panic();
255 }
256 }
257 #endif
258
bl31_plat_arch_setup(void)259 void bl31_plat_arch_setup(void)
260 {
261 const mmap_region_t bl_regions[] = {
262 MAP_BL31_TOTAL,
263 MAP_BL31_RO,
264 #if USE_COHERENT_MEM
265 MAP_BL_COHERENT_RAM,
266 #endif
267 #if ENABLE_RME
268 MAP_GPT_L0_REGION,
269 MAP_GPT_L1_REGION,
270 MAP_RMM_SHARED_MEM,
271 #endif
272 {0}
273 };
274
275 setup_page_tables(bl_regions, plat_qemu_get_mmap());
276
277 enable_mmu_el3(0);
278
279 #if ENABLE_RME
280 /* Initialise and enable granule protection after MMU. */
281 bl31_plat_gpt_setup();
282
283 /*
284 * Initialise Granule Protection library and enable GPC for the primary
285 * processor. The tables have already been initialized by a previous BL
286 * stage, so there is no need to provide any PAS here. This function
287 * sets up pointers to those tables.
288 */
289 if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) {
290 ERROR("gpt_runtime_init() failed!\n");
291 panic();
292 }
293 #endif /* ENABLE_RME */
294
295 }
296
qemu_gpio_init(void)297 static void qemu_gpio_init(void)
298 {
299 #ifdef SECURE_GPIO_BASE
300 pl061_gpio_init();
301 pl061_gpio_register(SECURE_GPIO_BASE, 0);
302 #endif
303 }
304
bl31_platform_setup(void)305 void bl31_platform_setup(void)
306 {
307 plat_qemu_gic_init();
308 qemu_gpio_init();
309 }
310
plat_get_syscnt_freq2(void)311 unsigned int plat_get_syscnt_freq2(void)
312 {
313 return read_cntfrq_el0();
314 }
315
316 /*******************************************************************************
317 * Return a pointer to the 'entry_point_info' structure of the next image
318 * for the security state specified. BL3-3 corresponds to the non-secure
319 * image type while BL3-2 corresponds to the secure image type. A NULL
320 * pointer is returned if the image does not exist.
321 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)322 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
323 {
324 entry_point_info_t *next_image_info;
325
326 assert(sec_state_is_valid(type));
327 if (type == NON_SECURE) {
328 next_image_info = &bl33_image_ep_info;
329 }
330 #if ENABLE_RME
331 else if (type == REALM) {
332 next_image_info = &rmm_image_ep_info;
333 }
334 #endif
335 else {
336 next_image_info = &bl32_image_ep_info;
337 }
338
339 /*
340 * None of the images on the ARM development platforms can have 0x0
341 * as the entrypoint
342 */
343 if (next_image_info->pc)
344 return next_image_info;
345 else
346 return NULL;
347 }
348
bl31_plat_runtime_setup(void)349 void bl31_plat_runtime_setup(void)
350 {
351 #if TRANSFER_LIST
352 if (bl31_tl) {
353 /*
354 * Relocate the TL from S to NS memory before EL3 exit
355 * to reflect all changes in TL done by BL32
356 */
357 if (!transfer_list_relocate(bl31_tl, (void *)FW_NS_HANDOFF_BASE,
358 bl31_tl->max_size))
359 ERROR("Relocate TL to NS memory failed\n");
360 }
361 #endif
362
363 console_flush();
364 console_switch_state(CONSOLE_FLAG_RUNTIME);
365 }
366