Merge "build(handoff)!: switch to LibTL submodule" into integration

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration

* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refacto

Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration

* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refactor(optee): guard handoff logic w/ build flag
feat(handoff): support libtl submodule builds

show more ...

refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER

refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER_LIST` guards, ensuring QEMU can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: I0be3773bf300b02cd3beccf738a021925e3c53c6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

show more ...

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transf

Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transfer entry ID for TPM event log
fix(qemu): fix register convention in BL31 for qemu
fix(handoff): fix register convention in opteed

show more ...

feat(qemu): hand off TPM event log via TL

If TRANSFER_LIST is enabled, hand off TPM event log via TL instead
of DT; otherwise fallback to legacy way if TRANSFER_LIST is off or
errors observed.

More

feat(qemu): hand off TPM event log via TL

If TRANSFER_LIST is enabled, hand off TPM event log via TL instead
of DT; otherwise fallback to legacy way if TRANSFER_LIST is off or
errors observed.

Moreover, for updating the TL from secure to non-secure
memory before existing EL3, replace memcpy with function
transfer_list_relocate() for more accuracy.

Change-Id: I1d6bcf573f91efe99380bc89195198a8583b1def
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

show more ...

fix(qemu): fix register convention in BL31 for qemu

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in

fix(qemu): fix register convention in BL31 for qemu

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in BL31.
As a result, a system panic observed during setup for BL32 when
TRANSFER_LIST is enabled due to unexpected arguments.
This patch is to fix this issue for qemu.

Change-Id: I42e581c5026f0f66d3b114204b4dff167a9bc6ae
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

show more ...

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

show more ...

feat(qemu-sbsa): configure GPT based on system RAM

The amount of memory supported by the SBSA platform is dynamic
and dependent on user input. Since the configuration of the GPT
needs to reflect th

feat(qemu-sbsa): configure GPT based on system RAM

The amount of memory supported by the SBSA platform is dynamic
and dependent on user input. Since the configuration of the GPT
needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
based on the information found in the device tree.

Change-Id: I5d1411ac00020b7b38a652ba2904c8a70fa64d18
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something mo

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something more appropriate and move
it to a header that make sense.

No change in functionality.

Change-Id: I7bd78b1fe70e2930c395ef0a097bfad3b1e55d3a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider phys

refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider physical address range can be supported.

No change in functionality.

Change-Id: I5b7b4968636d61929ad6ebdc05c389291cf510b1
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access

refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access generates a GPT check fault because the device tree
area is configure as non-secure RAM and the access is made from secure
EL3.

We could change the device tree memory area configuration in a way that
it is accessible from BL31, but that would require another configuration
of the GPT before going to BL33.

Since BL2 and BL31 are both running at EL3, a better solution is simply
move the GPT configuration and enabling to BL31, after the device tree
has been probed.

No change in functionality.

Change-Id: Ifa01c50164268b993d563c32e4e42140259c44e2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
[Added changelog description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

show more ...

Merge "refactor(qemu): do not hardcode counter frequency" into integration

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

show more ...

Merge "refactor(qemu): console runtime switch on bl31 exit" into integration

refactor(qemu): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A pl

refactor(qemu): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the QEMU platform only.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I6188d73dd3f3c97f41bb25de543f8c46a972adf0

show more ...

Merge changes from topic "tl_bl31_bl32" into integration

* changes:
feat(qemu): enable transfer list to BL31/32
feat(optee): enable transfer list in opteed

feat(qemu): enable transfer list to BL31/32

Enable handoff to BL31 and BL32 using transfer list.
Encode TL_TAG_OPTEE_PAGABLE_PART as transfer entry.
Fallback to default handoff args when transfer li

feat(qemu): enable transfer list to BL31/32

Enable handoff to BL31 and BL32 using transfer list.
Encode TL_TAG_OPTEE_PAGABLE_PART as transfer entry.
Fallback to default handoff args when transfer list is disabled or
fails to archieve args from transfer entries.
Refactor handoff from BL2 to BL33.
Minor fixes of comment style.

Change-Id: I55d92ca7f5c4727bacc9725a7216c0ac70d16aec
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

show more ...

Merge changes from topic "qemu-rme" into integration

* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setu

Merge changes from topic "qemu-rme" into integration

* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setup memory map for RME
feat(qemu): update mapping types for RME
feat(qemu): use mock attestation functions for RME
fix(qemu): increase max FIP size

show more ...

feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

C

feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

Change-Id: I15863410b1e505aa502276b339b22a2ddcb0b745
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff93

feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff9307550e6d26d432674779a
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

feat(qemu): setup memory map for RME

Reserve some space in DRAM for RMM, and some space in SRAM for the GPT
tables. Create the page table mappings.

Change-Id: I3822e7e505e86eb0fa15b1b5b6298e4122b17

feat(qemu): setup memory map for RME

Reserve some space in DRAM for RMM, and some space in SRAM for the GPT
tables. Create the page table mappings.

Change-Id: I3822e7e505e86eb0fa15b1b5b6298e4122b17181
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

Merge changes from topic "version/0.1-gic" into integration

* changes:
feat(qemu-sbsa): handle GIC base
feat(qemu-sbsa): handle platform version