1 /* 2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/pl061_gpio.h> 13 #include <lib/gpt_rme/gpt_rme.h> 14 #if TRANSFER_LIST 15 #include <transfer_list.h> 16 #endif 17 #include <plat/common/platform.h> 18 #if ENABLE_RME 19 #ifdef PLAT_qemu 20 #include <qemu_pas_def.h> 21 #elif PLAT_qemu_sbsa 22 #include <qemu_sbsa_pas_def.h> 23 #endif /* PLAT_qemu */ 24 #endif /* ENABLE_RME */ 25 #ifdef PLAT_qemu_sbsa 26 #include <sbsa_platform.h> 27 #endif 28 29 #include "qemu_private.h" 30 31 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 32 BL31_BASE, \ 33 BL31_END - BL31_BASE, \ 34 MT_MEMORY | MT_RW | EL3_PAS) 35 #define MAP_BL31_RO MAP_REGION_FLAT( \ 36 BL_CODE_BASE, \ 37 BL_CODE_END - BL_CODE_BASE, \ 38 MT_CODE | EL3_PAS), \ 39 MAP_REGION_FLAT( \ 40 BL_RO_DATA_BASE, \ 41 BL_RO_DATA_END \ 42 - BL_RO_DATA_BASE, \ 43 MT_RO_DATA | EL3_PAS) 44 45 #if USE_COHERENT_MEM 46 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 47 BL_COHERENT_RAM_BASE, \ 48 BL_COHERENT_RAM_END \ 49 - BL_COHERENT_RAM_BASE, \ 50 MT_DEVICE | MT_RW | EL3_PAS) 51 #endif 52 53 #if ENABLE_RME 54 #if (RME_GPT_BITLOCK_BLOCK == 0) 55 #define BITLOCK_BASE UL(0) 56 #define BITLOCK_SIZE UL(0) 57 #else 58 59 /* 60 * Number of bitlock_t entries in the gpt_bitlock array for this platform's 61 * Protected Physical Size. One 8-bit bitlock_t entry covers 62 * 8 * RME_GPT_BITLOCK_BLOCK * 512MB. 63 */ 64 #if (PLAT_QEMU_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 65 #define BITLOCKS_NUM (PLAT_QEMU_PPS / \ 66 (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 67 #else 68 #define BITLOCKS_NUM 1 69 #endif 70 71 static bitlock_t gpt_bitlock[BITLOCKS_NUM]; 72 #define BITLOCK_BASE (uintptr_t)gpt_bitlock 73 #define BITLOCK_SIZE sizeof(gpt_bitlock) 74 #endif /* RME_GPT_BITLOCK_BLOCK */ 75 #endif /* ENABLE_RME */ 76 77 /* 78 * Placeholder variables for copying the arguments that have been passed to 79 * BL3-1 from BL2. 80 */ 81 static entry_point_info_t bl32_image_ep_info; 82 static entry_point_info_t bl33_image_ep_info; 83 #if ENABLE_RME 84 static entry_point_info_t rmm_image_ep_info; 85 #endif 86 static struct transfer_list_header __maybe_unused *bl31_tl; 87 88 /******************************************************************************* 89 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 90 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 91 * they are lost (potentially). This needs to be done before the MMU is 92 * initialized so that the memory layout can be used while creating page 93 * tables. BL2 has flushed this information to memory, so we are guaranteed 94 * to pick up good data. 95 ******************************************************************************/ 96 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 97 u_register_t arg2, u_register_t arg3) 98 { 99 bool __maybe_unused is64 = false; 100 uint64_t __maybe_unused hval; 101 102 /* 103 * There's a crash on QEMU when initializing SVE in BL31 if FP 104 * traps is enabled in EL3. So disable it until we have permenant 105 * fix for the QEMU platform. 106 */ 107 disable_fpregs_traps_el3(); 108 109 /* Initialize the console to provide early debug support */ 110 qemu_console_init(); 111 112 /* Platform names have to be lowercase. */ 113 #ifdef PLAT_qemu_sbsa 114 sbsa_platform_init(); 115 #endif 116 117 /* 118 * Check params passed from BL2 119 */ 120 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 121 122 assert(params_from_bl2); 123 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 124 assert(params_from_bl2->h.version >= VERSION_2); 125 126 bl_params_node_t *bl_params = params_from_bl2->head; 127 128 /* 129 * Copy BL33, BL32 and RMM (if present), entry point information. 130 * They are stored in Secure RAM, in BL2's address space. 131 */ 132 while (bl_params) { 133 #if defined(__aarch64__) && TRANSFER_LIST 134 if (bl_params->image_id == BL31_IMAGE_ID && 135 GET_RW(bl_params->ep_info->spsr) == MODE_RW_64) 136 is64 = true; 137 #endif /* defined(__aarch64__) && TRANSFER_LIST */ 138 if (bl_params->image_id == BL32_IMAGE_ID) 139 bl32_image_ep_info = *bl_params->ep_info; 140 141 #if ENABLE_RME 142 if (bl_params->image_id == RMM_IMAGE_ID) 143 rmm_image_ep_info = *bl_params->ep_info; 144 #endif 145 146 if (bl_params->image_id == BL33_IMAGE_ID) 147 bl33_image_ep_info = *bl_params->ep_info; 148 149 bl_params = bl_params->next_params_info; 150 } 151 152 if (!bl33_image_ep_info.pc) 153 panic(); 154 #if ENABLE_RME 155 if (!rmm_image_ep_info.pc) 156 panic(); 157 #endif 158 159 #if TRANSFER_LIST 160 if (!transfer_list_check_header((void *)arg3)) 161 return; 162 163 if (is64) 164 hval = TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 165 else 166 hval = TRANSFER_LIST_HANDOFF_R1_VALUE(REGISTER_CONVENTION_VERSION); 167 168 if (arg1 != hval) 169 return; 170 #endif 171 172 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ 173 } 174 175 #if ENABLE_RME 176 #if PLAT_qemu 177 /* 178 * The GPT library might modify the gpt regions structure to optimize 179 * the layout, so the array cannot be constant. 180 */ 181 static pas_region_t pas_regions[] = { 182 QEMU_PAS_ROOT, 183 QEMU_PAS_SECURE, 184 QEMU_PAS_GPTS, 185 QEMU_PAS_NS0, 186 QEMU_PAS_REALM, 187 QEMU_PAS_NS1, 188 }; 189 190 static inline void bl31_adjust_pas_regions(void) {} 191 #elif PLAT_qemu_sbsa 192 /* 193 * The GPT library might modify the gpt regions structure to optimize 194 * the layout, so the array cannot be constant. 195 */ 196 static pas_region_t pas_regions[] = { 197 QEMU_PAS_ROOT, 198 QEMU_PAS_SECURE, 199 QEMU_PAS_GPTS, 200 QEMU_PAS_REALM, 201 QEMU_PAS_NS0, 202 }; 203 204 static void bl31_adjust_pas_regions(void) 205 { 206 uint64_t base_addr = 0, total_size = 0; 207 struct platform_memory_data data; 208 uint32_t node; 209 210 /* 211 * The amount of memory supported by the SBSA platform is dynamic 212 * and dependent on user input. Since the configuration of the GPT 213 * needs to reflect the system memory, QEMU_PAS_NS0 needs to be set 214 * based on the information found in the device tree. 215 */ 216 217 for (node = 0; node < sbsa_platform_num_memnodes(); node++) { 218 data = sbsa_platform_memory_node(node); 219 220 if (data.nodeid == 0) { 221 base_addr = data.addr_base; 222 } 223 224 total_size += data.addr_size; 225 } 226 227 /* Index '4' correspond to QEMU_PAS_NS0, see pas_regions[] above */ 228 pas_regions[4].base_pa = base_addr; 229 pas_regions[4].size = total_size; 230 } 231 #endif /* PLAT_qemu */ 232 233 static void bl31_plat_gpt_setup(void) 234 { 235 /* 236 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry 237 * covering 1GB (currently the only supported option), then covering 238 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the 239 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA). 240 */ 241 if (gpt_init_l0_tables(PLAT_QEMU_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE, 242 PLAT_QEMU_L0_GPT_SIZE) < 0) { 243 ERROR("gpt_init_l0_tables() failed!\n"); 244 panic(); 245 } 246 247 bl31_adjust_pas_regions(); 248 249 /* Carve out defined PAS ranges. */ 250 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 251 PLAT_QEMU_L1_GPT_BASE, 252 PLAT_QEMU_L1_GPT_SIZE, 253 pas_regions, 254 (unsigned int)(sizeof(pas_regions) / 255 sizeof(pas_region_t))) < 0) { 256 ERROR("gpt_init_pas_l1_tables() failed!\n"); 257 panic(); 258 } 259 260 INFO("Enabling Granule Protection Checks\n"); 261 if (gpt_enable() < 0) { 262 ERROR("gpt_enable() failed!\n"); 263 panic(); 264 } 265 } 266 #endif 267 268 void bl31_plat_arch_setup(void) 269 { 270 const mmap_region_t bl_regions[] = { 271 MAP_BL31_TOTAL, 272 MAP_BL31_RO, 273 #if USE_COHERENT_MEM 274 MAP_BL_COHERENT_RAM, 275 #endif 276 #if ENABLE_RME 277 MAP_GPT_L0_REGION, 278 MAP_GPT_L1_REGION, 279 MAP_RMM_SHARED_MEM, 280 #endif 281 {0} 282 }; 283 284 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 285 286 enable_mmu_el3(0); 287 288 #if ENABLE_RME 289 /* Initialise and enable granule protection after MMU. */ 290 bl31_plat_gpt_setup(); 291 292 /* 293 * Initialise Granule Protection library and enable GPC for the primary 294 * processor. The tables have already been initialized by a previous BL 295 * stage, so there is no need to provide any PAS here. This function 296 * sets up pointers to those tables. 297 */ 298 if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) { 299 ERROR("gpt_runtime_init() failed!\n"); 300 panic(); 301 } 302 #endif /* ENABLE_RME */ 303 304 } 305 306 static void qemu_gpio_init(void) 307 { 308 #ifdef SECURE_GPIO_BASE 309 pl061_gpio_init(); 310 pl061_gpio_register(SECURE_GPIO_BASE, 0); 311 #endif 312 } 313 314 void bl31_platform_setup(void) 315 { 316 plat_qemu_gic_init(); 317 qemu_gpio_init(); 318 } 319 320 unsigned int plat_get_syscnt_freq2(void) 321 { 322 return read_cntfrq_el0(); 323 } 324 325 /******************************************************************************* 326 * Return a pointer to the 'entry_point_info' structure of the next image 327 * for the security state specified. BL3-3 corresponds to the non-secure 328 * image type while BL3-2 corresponds to the secure image type. A NULL 329 * pointer is returned if the image does not exist. 330 ******************************************************************************/ 331 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 332 { 333 entry_point_info_t *next_image_info; 334 335 assert(sec_state_is_valid(type)); 336 if (type == NON_SECURE) { 337 next_image_info = &bl33_image_ep_info; 338 } 339 #if ENABLE_RME 340 else if (type == REALM) { 341 next_image_info = &rmm_image_ep_info; 342 } 343 #endif 344 else { 345 next_image_info = &bl32_image_ep_info; 346 } 347 348 /* 349 * None of the images on the ARM development platforms can have 0x0 350 * as the entrypoint 351 */ 352 if (next_image_info->pc) 353 return next_image_info; 354 else 355 return NULL; 356 } 357 358 void bl31_plat_runtime_setup(void) 359 { 360 #if TRANSFER_LIST 361 if (bl31_tl) { 362 /* 363 * Relocate the TL from S to NS memory before EL3 exit 364 * to reflect all changes in TL done by BL32 365 */ 366 if (!transfer_list_relocate(bl31_tl, (void *)FW_NS_HANDOFF_BASE, 367 bl31_tl->max_size)) 368 ERROR("Relocate TL to NS memory failed\n"); 369 } 370 #endif 371 372 console_flush(); 373 console_switch_state(CONSOLE_FLAG_RUNTIME); 374 } 375