1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cci.h> 12 #include <common/debug.h> 13 #include <dcfg.h> 14 #ifdef I2C_INIT 15 #include <i2c.h> 16 #endif 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <ls_interconnect.h> 20 #if TRUSTED_BOARD_BOOT 21 #include <nxp_smmu.h> 22 #endif 23 #include <nxp_timer.h> 24 #include <plat_console.h> 25 #include <plat_gic.h> 26 #include <plat_tzc400.h> 27 #include <pmu.h> 28 #if defined(NXP_SFP_ENABLED) 29 #include <sfp.h> 30 #endif 31 32 #include <errata.h> 33 #ifdef CONFIG_OCRAM_ECC_EN 34 #include <ocram.h> 35 #endif 36 #include <plat_common.h> 37 #include <platform_def.h> 38 #include <soc.h> 39 40 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; 41 static struct soc_type soc_list[] = { 42 SOC_ENTRY(LS1044A, LS1044A, 1, 4), 43 SOC_ENTRY(LS1044AE, LS1044AE, 1, 4), 44 SOC_ENTRY(LS1048A, LS1048A, 1, 4), 45 SOC_ENTRY(LS1048AE, LS1048AE, 1, 4), 46 SOC_ENTRY(LS1084A, LS1084A, 2, 4), 47 SOC_ENTRY(LS1084AE, LS1084AE, 2, 4), 48 SOC_ENTRY(LS1088A, LS1088A, 2, 4), 49 SOC_ENTRY(LS1088AE, LS1088AE, 2, 4), 50 }; 51 52 static dcfg_init_info_t dcfg_init_data = { 53 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 54 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 55 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 56 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 57 }; 58 59 /* 60 * This function dynamically constructs the topology according to 61 * SoC Flavor and returns it. 62 */ 63 const unsigned char *plat_get_power_domain_tree_desc(void) 64 { 65 unsigned int i; 66 uint8_t num_clusters, cores_per_cluster; 67 68 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 69 70 /* 71 * The highest level is the system level. The next level is constituted 72 * by clusters and then cores in clusters. 73 */ 74 _power_domain_tree_desc[0] = 1; 75 _power_domain_tree_desc[1] = num_clusters; 76 77 for (i = 0; i < _power_domain_tree_desc[1]; i++) { 78 _power_domain_tree_desc[i + 2] = cores_per_cluster; 79 } 80 81 82 return _power_domain_tree_desc; 83 } 84 85 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 86 assert_invalid_ls1088a_cluster_count); 87 88 /* 89 * This function returns the core count within the cluster corresponding to 90 * `mpidr`. 91 */ 92 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 93 { 94 return CORES_PER_CLUSTER; 95 } 96 97 /* 98 * This function returns the total number of cores in the SoC 99 */ 100 unsigned int get_tot_num_cores(void) 101 { 102 uint8_t num_clusters, cores_per_cluster; 103 104 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 105 106 return (num_clusters * cores_per_cluster); 107 } 108 109 /* 110 * This function returns the PMU IDLE Cluster mask. 111 */ 112 unsigned int get_pmu_idle_cluster_mask(void) 113 { 114 uint8_t num_clusters, cores_per_cluster; 115 116 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 117 118 return ((1 << num_clusters) - 2); 119 } 120 121 /* 122 * This function returns the PMU Flush Cluster mask. 123 */ 124 unsigned int get_pmu_flush_cluster_mask(void) 125 { 126 uint8_t num_clusters, cores_per_cluster; 127 128 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 129 130 return ((1 << num_clusters) - 2); 131 } 132 133 /* 134 * This function returns the PMU IDLE Core mask. 135 */ 136 unsigned int get_pmu_idle_core_mask(void) 137 { 138 return ((1 << get_tot_num_cores()) - 2); 139 } 140 141 #ifdef IMAGE_BL2 142 143 void soc_bl2_prepare_exit(void) 144 { 145 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 146 set_sfp_wr_disable(); 147 #endif 148 } 149 150 void soc_preload_setup(void) 151 { 152 153 } 154 155 /* 156 * This function returns the boot device based on RCW_SRC 157 */ 158 enum boot_device get_boot_dev(void) 159 { 160 enum boot_device src = BOOT_DEVICE_NONE; 161 uint32_t porsr1; 162 uint32_t rcw_src, val; 163 164 porsr1 = read_reg_porsr1(); 165 166 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 167 168 /* RCW SRC NOR */ 169 val = rcw_src & RCW_SRC_TYPE_MASK; 170 if (val == NOR_16B_VAL) { 171 src = BOOT_DEVICE_IFC_NOR; 172 INFO("RCW BOOT SRC is IFC NOR\n"); 173 } else { 174 val = rcw_src & RCW_SRC_SERIAL_MASK; 175 switch (val) { 176 case QSPI_VAL: 177 src = BOOT_DEVICE_QSPI; 178 INFO("RCW BOOT SRC is QSPI\n"); 179 break; 180 case SDHC_VAL: 181 src = BOOT_DEVICE_EMMC; 182 INFO("RCW BOOT SRC is SD/EMMC\n"); 183 break; 184 case EMMC_VAL: 185 src = BOOT_DEVICE_EMMC; 186 INFO("RCW BOOT SRC is SD/EMMC\n"); 187 break; 188 default: 189 src = BOOT_DEVICE_NONE; 190 } 191 } 192 193 return src; 194 } 195 196 /* 197 * This function sets up access permissions on memory regions 198 */ 199 void soc_mem_access(void) 200 { 201 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 202 int i = 0; 203 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 204 int dram_idx, index = 1; 205 206 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; 207 dram_idx++) { 208 if (info_dram_regions->region[i].size == 0) { 209 ERROR("DDR init failure, or"); 210 ERROR("DRAM regions not populated correctly.\n"); 211 break; 212 } 213 214 index = populate_tzc400_reg_list(tzc400_reg_list, 215 dram_idx, index, 216 info_dram_regions->region[dram_idx].addr, 217 info_dram_regions->region[dram_idx].size, 218 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 219 } 220 221 mem_access_setup(NXP_TZC_ADDR, index, 222 tzc400_reg_list); 223 } 224 225 /* 226 * This function implements soc specific erratum 227 * This is called before DDR is initialized or MMU is enabled 228 */ 229 void soc_early_init(void) 230 { 231 enum boot_device dev; 232 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 233 234 #ifdef CONFIG_OCRAM_ECC_EN 235 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 236 #endif 237 dcfg_init(&dcfg_init_data); 238 #if LOG_LEVEL > 0 239 /* Initialize the console to provide early debug support */ 240 plat_console_init(NXP_CONSOLE_ADDR, 241 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 242 #endif 243 enable_timer_base_to_cluster(NXP_PMU_ADDR); 244 enable_core_tb(NXP_PMU_ADDR); 245 246 /* 247 * Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE) 248 * as dma of sd 249 */ 250 dev = get_boot_dev(); 251 if (dev == BOOT_DEVICE_EMMC) { 252 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 253 NXP_SD_BLOCK_BUF_SIZE, 254 MT_DEVICE | MT_RW | MT_NS); 255 } 256 257 #if TRUSTED_BOARD_BOOT 258 uint32_t mode; 259 260 sfp_init(NXP_SFP_ADDR); 261 /* 262 * For secure boot disable SMMU. 263 * Later when platform security policy comes in picture, 264 * this might get modified based on the policy 265 */ 266 if (check_boot_mode_secure(&mode) == true) { 267 bypass_smmu(NXP_SMMU_ADDR); 268 } 269 270 /* 271 * For Mbedtls currently crypto is not supported via CAAM 272 * enable it when that support is there. In tbbr.mk 273 * the CAAM_INTEG is set as 0. 274 */ 275 #ifndef MBEDTLS_X509 276 /* Initialize the crypto accelerator if enabled */ 277 if (is_sec_enabled() == false) { 278 INFO("SEC is disabled.\n"); 279 } else { 280 sec_init(NXP_CAAM_ADDR); 281 } 282 #endif 283 #endif 284 285 soc_errata(); 286 287 delay_timer_init(NXP_TIMER_ADDR); 288 i2c_init(NXP_I2C_ADDR); 289 dram_regions_info->total_dram_size = init_ddr(); 290 } 291 #else /* !IMAGE_BL2 */ 292 293 void soc_early_platform_setup2(void) 294 { 295 dcfg_init(&dcfg_init_data); 296 /* 297 * Initialize system level generic timer for Socs 298 */ 299 delay_timer_init(NXP_TIMER_ADDR); 300 301 #if LOG_LEVEL > 0 302 /* Initialize the console to provide early debug support */ 303 plat_console_init(NXP_CONSOLE_ADDR, 304 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 305 #endif 306 } 307 308 void soc_platform_setup(void) 309 { 310 /* Initialize the GIC driver, cpu and distributor interfaces */ 311 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 312 static interrupt_prop_t ls_interrupt_props[] = { 313 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 314 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 315 }; 316 317 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 318 PLATFORM_CORE_COUNT, 319 ls_interrupt_props, 320 ARRAY_SIZE(ls_interrupt_props), 321 target_mask_array, 322 plat_core_pos); 323 324 plat_ls_gic_init(); 325 enable_init_timer(); 326 } 327 328 /* 329 * This function initializes the soc from the BL31 module 330 */ 331 void soc_init(void) 332 { 333 uint8_t num_clusters, cores_per_cluster; 334 335 /* low-level init of the soc */ 336 soc_init_lowlevel(); 337 _init_global_data(); 338 soc_init_percpu(); 339 _initialize_psci(); 340 341 /* 342 * Initialize Interconnect for this cluster during cold boot. 343 * No need for locks as no other CPU is active. 344 */ 345 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 346 347 /* 348 * Enable Interconnect coherency for the primary CPU's cluster. 349 */ 350 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 351 plat_ls_interconnect_enter_coherency(num_clusters); 352 353 /* set platform security policies */ 354 _set_platform_security(); 355 356 /* Initialize the crypto accelerator if enabled */ 357 if (is_sec_enabled() == false) { 358 INFO("SEC is disabled.\n"); 359 } else { 360 sec_init(NXP_CAAM_ADDR); 361 } 362 } 363 364 void soc_runtime_setup(void) 365 { 366 367 } 368 #endif /* IMAGE_BL2 */ 369 370 /* 371 * Function to return the SoC SYS CLK 372 */ 373 unsigned int get_sys_clk(void) 374 { 375 return NXP_SYSCLK_FREQ; 376 } 377 378 /* 379 * Function returns the base counter frequency 380 * after reading the first entry at CNTFID0 (0x20 offset). 381 * 382 * Function is used by: 383 * 1. ARM common code for PSCI management. 384 * 2. ARM Generic Timer init. 385 */ 386 unsigned int plat_get_syscnt_freq2(void) 387 { 388 unsigned int counter_base_frequency; 389 /* 390 * Below register specifies the base frequency of the system counter. 391 * As per NXP Board Manuals: 392 * The system counter always works with SYS_REF_CLK/4 frequency clock. 393 */ 394 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 395 396 return counter_base_frequency; 397 } 398