1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cci.h> 12 #include <common/debug.h> 13 #include <dcfg.h> 14 #ifdef I2C_INIT 15 #include <i2c.h> 16 #endif 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <ls_interconnect.h> 20 #include <nxp_smmu.h> 21 #include <nxp_timer.h> 22 #include <plat_console.h> 23 #include <plat_gic.h> 24 #include <plat_tzc400.h> 25 #include <pmu.h> 26 #if defined(NXP_SFP_ENABLED) 27 #include <sfp.h> 28 #endif 29 30 #include <errata.h> 31 #ifdef CONFIG_OCRAM_ECC_EN 32 #include <ocram.h> 33 #endif 34 #include <plat_common.h> 35 #include <platform_def.h> 36 #include <soc.h> 37 38 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; 39 static struct soc_type soc_list[] = { 40 SOC_ENTRY(LS1044A, LS1044A, 1, 4), 41 SOC_ENTRY(LS1044AE, LS1044AE, 1, 4), 42 SOC_ENTRY(LS1048A, LS1048A, 1, 4), 43 SOC_ENTRY(LS1048AE, LS1048AE, 1, 4), 44 SOC_ENTRY(LS1084A, LS1084A, 2, 4), 45 SOC_ENTRY(LS1084AE, LS1084AE, 2, 4), 46 SOC_ENTRY(LS1088A, LS1088A, 2, 4), 47 SOC_ENTRY(LS1088AE, LS1088AE, 2, 4), 48 }; 49 50 static dcfg_init_info_t dcfg_init_data = { 51 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 52 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 53 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 54 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 55 }; 56 57 /* 58 * This function dynamically constructs the topology according to 59 * SoC Flavor and returns it. 60 */ 61 const unsigned char *plat_get_power_domain_tree_desc(void) 62 { 63 unsigned int i; 64 uint8_t num_clusters, cores_per_cluster; 65 66 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 67 68 /* 69 * The highest level is the system level. The next level is constituted 70 * by clusters and then cores in clusters. 71 */ 72 _power_domain_tree_desc[0] = 1; 73 _power_domain_tree_desc[1] = num_clusters; 74 75 for (i = 0; i < _power_domain_tree_desc[1]; i++) { 76 _power_domain_tree_desc[i + 2] = cores_per_cluster; 77 } 78 79 80 return _power_domain_tree_desc; 81 } 82 83 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 84 assert_invalid_ls1088a_cluster_count); 85 86 /* 87 * This function returns the core count within the cluster corresponding to 88 * `mpidr`. 89 */ 90 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 91 { 92 return CORES_PER_CLUSTER; 93 } 94 95 /* 96 * This function returns the total number of cores in the SoC 97 */ 98 unsigned int get_tot_num_cores(void) 99 { 100 uint8_t num_clusters, cores_per_cluster; 101 102 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 103 104 return (num_clusters * cores_per_cluster); 105 } 106 107 /* 108 * This function returns the PMU IDLE Cluster mask. 109 */ 110 unsigned int get_pmu_idle_cluster_mask(void) 111 { 112 uint8_t num_clusters, cores_per_cluster; 113 114 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 115 116 return ((1 << num_clusters) - 2); 117 } 118 119 /* 120 * This function returns the PMU Flush Cluster mask. 121 */ 122 unsigned int get_pmu_flush_cluster_mask(void) 123 { 124 uint8_t num_clusters, cores_per_cluster; 125 126 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 127 128 return ((1 << num_clusters) - 2); 129 } 130 131 /* 132 * This function returns the PMU IDLE Core mask. 133 */ 134 unsigned int get_pmu_idle_core_mask(void) 135 { 136 return ((1 << get_tot_num_cores()) - 2); 137 } 138 139 #ifdef IMAGE_BL2 140 141 void soc_bl2_prepare_exit(void) 142 { 143 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 144 set_sfp_wr_disable(); 145 #endif 146 } 147 148 void soc_preload_setup(void) 149 { 150 151 } 152 153 /* 154 * This function returns the boot device based on RCW_SRC 155 */ 156 enum boot_device get_boot_dev(void) 157 { 158 enum boot_device src = BOOT_DEVICE_NONE; 159 uint32_t porsr1; 160 uint32_t rcw_src, val; 161 162 porsr1 = read_reg_porsr1(); 163 164 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 165 166 /* RCW SRC NOR */ 167 val = rcw_src & RCW_SRC_TYPE_MASK; 168 if (val == NOR_16B_VAL) { 169 src = BOOT_DEVICE_IFC_NOR; 170 INFO("RCW BOOT SRC is IFC NOR\n"); 171 } else { 172 val = rcw_src & RCW_SRC_SERIAL_MASK; 173 switch (val) { 174 case QSPI_VAL: 175 src = BOOT_DEVICE_QSPI; 176 INFO("RCW BOOT SRC is QSPI\n"); 177 break; 178 case SDHC_VAL: 179 src = BOOT_DEVICE_EMMC; 180 INFO("RCW BOOT SRC is SD/EMMC\n"); 181 break; 182 case EMMC_VAL: 183 src = BOOT_DEVICE_EMMC; 184 INFO("RCW BOOT SRC is SD/EMMC\n"); 185 break; 186 default: 187 src = BOOT_DEVICE_NONE; 188 } 189 } 190 191 return src; 192 } 193 194 /* 195 * This function sets up access permissions on memory regions 196 */ 197 void soc_mem_access(void) 198 { 199 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 200 int i = 0; 201 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 202 int dram_idx, index = 1; 203 204 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; 205 dram_idx++) { 206 if (info_dram_regions->region[i].size == 0) { 207 ERROR("DDR init failure, or"); 208 ERROR("DRAM regions not populated correctly.\n"); 209 break; 210 } 211 212 index = populate_tzc400_reg_list(tzc400_reg_list, 213 dram_idx, index, 214 info_dram_regions->region[dram_idx].addr, 215 info_dram_regions->region[dram_idx].size, 216 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 217 } 218 219 mem_access_setup(NXP_TZC_ADDR, index, 220 tzc400_reg_list); 221 } 222 223 /* 224 * This function implements soc specific erratum 225 * This is called before DDR is initialized or MMU is enabled 226 */ 227 void soc_early_init(void) 228 { 229 enum boot_device dev; 230 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 231 232 #ifdef CONFIG_OCRAM_ECC_EN 233 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 234 #endif 235 dcfg_init(&dcfg_init_data); 236 #if LOG_LEVEL > 0 237 /* Initialize the console to provide early debug support */ 238 plat_console_init(NXP_CONSOLE_ADDR, 239 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 240 #endif 241 enable_timer_base_to_cluster(NXP_PMU_ADDR); 242 enable_core_tb(NXP_PMU_ADDR); 243 244 /* 245 * Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE) 246 * as dma of sd 247 */ 248 dev = get_boot_dev(); 249 if (dev == BOOT_DEVICE_EMMC) { 250 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 251 NXP_SD_BLOCK_BUF_SIZE, 252 MT_DEVICE | MT_RW | MT_NS); 253 } 254 255 /* 256 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. 257 */ 258 smmu_cache_unlock(NXP_SMMU_ADDR); 259 INFO("SMMU Cache Unlocking is Configured.\n"); 260 261 #if TRUSTED_BOARD_BOOT 262 uint32_t mode; 263 264 sfp_init(NXP_SFP_ADDR); 265 /* 266 * For secure boot disable SMMU. 267 * Later when platform security policy comes in picture, 268 * this might get modified based on the policy 269 */ 270 if (check_boot_mode_secure(&mode) == true) { 271 bypass_smmu(NXP_SMMU_ADDR); 272 } 273 274 /* 275 * For Mbedtls currently crypto is not supported via CAAM 276 * enable it when that support is there. In tbbr.mk 277 * the CAAM_INTEG is set as 0. 278 */ 279 #ifndef MBEDTLS_X509 280 /* Initialize the crypto accelerator if enabled */ 281 if (is_sec_enabled() == false) { 282 INFO("SEC is disabled.\n"); 283 } else { 284 sec_init(NXP_CAAM_ADDR); 285 } 286 #endif 287 #endif 288 289 soc_errata(); 290 291 delay_timer_init(NXP_TIMER_ADDR); 292 i2c_init(NXP_I2C_ADDR); 293 dram_regions_info->total_dram_size = init_ddr(); 294 } 295 #else /* !IMAGE_BL2 */ 296 297 void soc_early_platform_setup2(void) 298 { 299 dcfg_init(&dcfg_init_data); 300 /* 301 * Initialize system level generic timer for Socs 302 */ 303 delay_timer_init(NXP_TIMER_ADDR); 304 305 #if LOG_LEVEL > 0 306 /* Initialize the console to provide early debug support */ 307 plat_console_init(NXP_CONSOLE_ADDR, 308 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 309 #endif 310 } 311 312 void soc_platform_setup(void) 313 { 314 /* Initialize the GIC driver, cpu and distributor interfaces */ 315 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 316 static interrupt_prop_t ls_interrupt_props[] = { 317 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 318 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 319 }; 320 321 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 322 PLATFORM_CORE_COUNT, 323 ls_interrupt_props, 324 ARRAY_SIZE(ls_interrupt_props), 325 target_mask_array, 326 plat_core_pos); 327 328 plat_ls_gic_init(); 329 enable_init_timer(); 330 } 331 332 /* 333 * This function initializes the soc from the BL31 module 334 */ 335 void soc_init(void) 336 { 337 uint8_t num_clusters, cores_per_cluster; 338 339 /* low-level init of the soc */ 340 soc_init_lowlevel(); 341 _init_global_data(); 342 soc_init_percpu(); 343 _initialize_psci(); 344 345 /* 346 * Initialize Interconnect for this cluster during cold boot. 347 * No need for locks as no other CPU is active. 348 */ 349 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 350 351 /* 352 * Enable Interconnect coherency for the primary CPU's cluster. 353 */ 354 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 355 plat_ls_interconnect_enter_coherency(num_clusters); 356 357 /* set platform security policies */ 358 _set_platform_security(); 359 360 /* Initialize the crypto accelerator if enabled */ 361 if (is_sec_enabled() == false) { 362 INFO("SEC is disabled.\n"); 363 } else { 364 sec_init(NXP_CAAM_ADDR); 365 } 366 } 367 368 void soc_runtime_setup(void) 369 { 370 371 } 372 #endif /* IMAGE_BL2 */ 373 374 /* 375 * Function to return the SoC SYS CLK 376 */ 377 unsigned int get_sys_clk(void) 378 { 379 return NXP_SYSCLK_FREQ; 380 } 381 382 /* 383 * Function returns the base counter frequency 384 * after reading the first entry at CNTFID0 (0x20 offset). 385 * 386 * Function is used by: 387 * 1. ARM common code for PSCI management. 388 * 2. ARM Generic Timer init. 389 */ 390 unsigned int plat_get_syscnt_freq2(void) 391 { 392 unsigned int counter_base_frequency; 393 /* 394 * Below register specifies the base frequency of the system counter. 395 * As per NXP Board Manuals: 396 * The system counter always works with SYS_REF_CLK/4 frequency clock. 397 */ 398 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 399 400 return counter_base_frequency; 401 } 402