1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <lib/mmio.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 #include <plat/common/platform.h> 14 #include <plat_console.h> 15 #include <s32cc-clk-drv.h> 16 17 #include <plat_io_storage.h> 18 #include <s32cc-bl-common.h> 19 #include <s32cc-ncore.h> 20 21 #define SIUL20_BASE UL(0x4009C000) 22 #define SIUL2_PC09_MSCR UL(0x4009C2E4) 23 #define SIUL2_PC10_MSCR UL(0x4009C2E8) 24 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) 25 26 #define LIN0_TX_MSCR_CFG U(0x00214001) 27 #define LIN0_RX_MSCR_CFG U(0x00094000) 28 #define LIN0_RX_IMCR_CFG U(0x00000002) 29 30 struct bl_load_info *plat_get_bl_image_load_info(void) 31 { 32 return get_bl_load_info_from_mem_params_desc(); 33 } 34 35 struct bl_params *plat_get_next_bl_params(void) 36 { 37 return get_next_bl_params_from_mem_params_desc(); 38 } 39 40 void plat_flush_next_bl_params(void) 41 { 42 flush_bl_params_desc(); 43 } 44 45 void bl2_platform_setup(void) 46 { 47 int ret; 48 49 ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE, 50 S32G_FIP_SIZE, 51 MT_MEMORY | MT_RW | MT_SECURE); 52 if (ret != 0) { 53 panic(); 54 } 55 } 56 57 static int s32g_mmap_siul2(void) 58 { 59 return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE, 60 MT_DEVICE | MT_RW | MT_SECURE); 61 } 62 63 static void linflex_config_pinctrl(void) 64 { 65 /* set PC09 - MSCR[41] - for UART0 TXD */ 66 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG); 67 /* set PC10 - MSCR[42] - for UART0 RXD */ 68 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG); 69 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */ 70 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG); 71 } 72 73 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 74 u_register_t arg2, u_register_t arg3) 75 { 76 int ret; 77 78 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which 79 * we have manually set during early BL2 boot. 80 */ 81 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU); 82 83 ncore_init(); 84 ncore_caiu_online(A53_CLUSTER0_CAIU); 85 86 ret = s32cc_init_core_clocks(); 87 if (ret != 0) { 88 panic(); 89 } 90 91 ret = s32cc_bl_mmu_setup(); 92 if (ret != 0) { 93 panic(); 94 } 95 96 ret = s32cc_init_early_clks(); 97 if (ret != 0) { 98 panic(); 99 } 100 101 ret = s32g_mmap_siul2(); 102 if (ret != 0) { 103 panic(); 104 } 105 106 linflex_config_pinctrl(); 107 console_s32g2_register(); 108 109 plat_s32g2_io_setup(); 110 } 111 112 void bl2_el3_plat_arch_setup(void) 113 { 114 } 115 116 int bl2_plat_handle_pre_image_load(unsigned int image_id) 117 { 118 const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id); 119 const struct image_info *img_info; 120 size_t size; 121 122 if (desc == NULL) { 123 return -EINVAL; 124 } 125 126 img_info = &desc->image_info; 127 128 if ((img_info == NULL) || (img_info->image_max_size == 0U)) { 129 return -EINVAL; 130 } 131 132 size = page_align(img_info->image_max_size, UP); 133 134 return mmap_add_dynamic_region(img_info->image_base, 135 img_info->image_base, 136 size, 137 MT_MEMORY | MT_RW | MT_SECURE); 138 } 139