1 /* 2 * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #include <psa/crypto_platform.h> 24 #include <psa/crypto_types.h> 25 #include <psa/crypto_values.h> 26 27 #ifdef PLATFORM_TEST_TFM_TESTSUITE 28 /* 29 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 30 * mbedTLS config option) so we need to provide an implementation of 31 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 32 * actually use any of external RNG and this function is only needed during 33 * the execution of TF-M testsuite during exporting the public part of the 34 * delegated attestation key. 35 */ 36 psa_status_t mbedtls_psa_external_get_random( 37 mbedtls_psa_external_random_context_t *context, 38 uint8_t *output, size_t output_size, 39 size_t *output_length) 40 { 41 for (size_t i = 0U; i < output_size; i++) { 42 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 43 } 44 45 *output_length = output_size; 46 47 return PSA_SUCCESS; 48 } 49 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 50 51 static scmi_channel_plat_info_t tc_scmi_plat_info[] = { 52 { 53 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 54 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 55 .db_preserve_mask = 0xfffffffe, 56 .db_modify_mask = 0x1, 57 .ring_doorbell = &mhuv2_ring_doorbell, 58 } 59 }; 60 61 void bl31_platform_setup(void) 62 { 63 tc_bl31_common_platform_setup(); 64 } 65 66 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id) 67 { 68 69 return &tc_scmi_plat_info[channel_id]; 70 71 } 72 73 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 74 u_register_t arg2, u_register_t arg3) 75 { 76 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 77 78 /* Fill the properties struct with the info from the config dtb */ 79 fconf_populate("FW_CONFIG", arg1); 80 } 81 82 #ifdef PLATFORM_TESTS 83 static __dead2 void tc_run_platform_tests(void) 84 { 85 int tests_failed; 86 87 printf("\nStarting platform tests...\n"); 88 89 #ifdef PLATFORM_TEST_NV_COUNTERS 90 tests_failed = nv_counter_test(); 91 #elif PLATFORM_TEST_ROTPK 92 tests_failed = rotpk_test(); 93 #elif PLATFORM_TEST_TFM_TESTSUITE 94 tests_failed = run_platform_tests(); 95 #endif 96 97 printf("Platform tests %s.\n", 98 (tests_failed != 0) ? "failed" : "succeeded"); 99 100 /* Suspend booting, no matter the tests outcome. */ 101 printf("Suspend booting...\n"); 102 plat_error_handler(-1); 103 } 104 #endif 105 106 void tc_bl31_common_platform_setup(void) 107 { 108 arm_bl31_platform_setup(); 109 110 #ifdef PLATFORM_TESTS 111 tc_run_platform_tests(); 112 #endif 113 } 114 115 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 116 { 117 return css_scmi_override_pm_ops(ops); 118 } 119 120 void __init bl31_plat_arch_setup(void) 121 { 122 arm_bl31_plat_arch_setup(); 123 124 /* HW_CONFIG was also loaded by BL2 */ 125 const struct dyn_cfg_dtb_info_t *hw_config_info; 126 127 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 128 assert(hw_config_info != NULL); 129 130 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 131 } 132 133 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 134 void tc_bl31_plat_runtime_setup(void) 135 { 136 arm_bl31_plat_runtime_setup(); 137 138 /* Start secure watchdog timer. */ 139 plat_arm_secure_wdt_start(); 140 } 141 142 void bl31_plat_runtime_setup(void) 143 { 144 tc_bl31_plat_runtime_setup(); 145 } 146 147 /* 148 * Platform handler for Group0 secure interrupt. 149 */ 150 int plat_spmd_handle_group0_interrupt(uint32_t intid) 151 { 152 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 153 if (intid == SBSA_SECURE_WDOG_INTID) { 154 /* Refresh the timer. */ 155 plat_arm_secure_wdt_refresh(); 156 157 return 0; 158 } 159 160 return -1; 161 } 162 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 163