1 /* 2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 #include <psa/error.h> 29 30 #include <plat/common/platform.h> 31 #include <tc_rse_comms.h> 32 33 #ifdef PLATFORM_TEST_TFM_TESTSUITE 34 /* 35 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 36 * mbedTLS config option) so we need to provide an implementation of 37 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 38 * actually use any of external RNG and this function is only needed during 39 * the execution of TF-M testsuite during exporting the public part of the 40 * delegated attestation key. 41 */ 42 psa_status_t mbedtls_psa_external_get_random( 43 mbedtls_psa_external_random_context_t *context, 44 uint8_t *output, size_t output_size, 45 size_t *output_length) 46 { 47 for (size_t i = 0U; i < output_size; i++) { 48 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 49 } 50 51 *output_length = output_size; 52 53 return PSA_SUCCESS; 54 } 55 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 56 57 #if TARGET_PLATFORM <= 2 58 static scmi_channel_plat_info_t tc_scmi_plat_info = { 59 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 60 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 61 .db_preserve_mask = 0xfffffffe, 62 .db_modify_mask = 0x1, 63 .ring_doorbell = &mhuv2_ring_doorbell, 64 }; 65 #elif TARGET_PLATFORM >= 3 66 static scmi_channel_plat_info_t tc_scmi_plat_info = { 67 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 68 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 69 .db_preserve_mask = 0xfffffffe, 70 .db_modify_mask = 0x1, 71 .ring_doorbell = &mhu_ring_doorbell, 72 }; 73 #endif 74 75 /* the bottom 3 AMU group 1 counters */ 76 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2)) 77 78 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = { 79 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 80 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 81 #if PLATFORM_CORE_COUNT == 14 82 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 83 MPMM_GEARS, MPMM_GEARS 84 #endif 85 }; 86 87 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 88 static void enable_ns_mcn_pmu(void) 89 { 90 /* 91 * Enable non-secure access to MCN PMU registers 92 */ 93 for (int i = 0; i < MCN_INSTANCES; i++) { 94 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + 95 MCN_SCR_OFFSET; 96 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 97 } 98 } 99 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 100 101 #if TARGET_PLATFORM == 3 102 static void set_mcn_slc_alloc_mode(void) 103 { 104 /* 105 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 106 * 0b01 (always alloc), configure both to 0b10 (use bus signal 107 * attribute from interface). 108 */ 109 for (int i = 0; i < MCN_INSTANCES; i++) { 110 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + 111 MPAM_SLCCFG_CTL_OFFSET; 112 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + 113 MPAM_SLCCFG_CTL_OFFSET; 114 115 mmio_clrsetbits_32(slccfg_ctl_ns, 116 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 117 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 118 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 119 mmio_clrsetbits_32(slccfg_ctl_s, 120 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 121 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 122 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 123 } 124 } 125 #endif 126 127 void bl31_platform_setup(void) 128 { 129 psa_status_t status; 130 131 tc_bl31_common_platform_setup(); 132 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 133 enable_ns_mcn_pmu(); 134 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 135 #if TARGET_PLATFORM == 3 136 set_mcn_slc_alloc_mode(); 137 plat_arm_ni_setup(NCI_BASE_ADDR); 138 #endif 139 140 /* Initialise RSE communication channel */ 141 status = plat_rse_comms_init(); 142 if (status != PSA_SUCCESS) { 143 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status); 144 } 145 } 146 147 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 148 { 149 150 return &tc_scmi_plat_info; 151 152 } 153 154 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 155 u_register_t arg2, u_register_t arg3) 156 { 157 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 158 159 /* Fill the properties struct with the info from the config dtb */ 160 fconf_populate("FW_CONFIG", arg1); 161 } 162 163 #ifdef PLATFORM_TESTS 164 static __dead2 void tc_run_platform_tests(void) 165 { 166 int tests_failed; 167 168 printf("\nStarting platform tests...\n"); 169 170 #ifdef PLATFORM_TEST_NV_COUNTERS 171 tests_failed = nv_counter_test(); 172 #elif PLATFORM_TEST_ROTPK 173 tests_failed = rotpk_test(); 174 #elif PLATFORM_TEST_TFM_TESTSUITE 175 tests_failed = run_platform_tests(); 176 #endif 177 178 printf("Platform tests %s.\n", 179 (tests_failed != 0) ? "failed" : "succeeded"); 180 181 /* Suspend booting, no matter the tests outcome. */ 182 printf("Suspend booting...\n"); 183 plat_error_handler(-1); 184 } 185 #endif 186 187 void tc_bl31_common_platform_setup(void) 188 { 189 arm_bl31_platform_setup(); 190 191 #ifdef PLATFORM_TESTS 192 tc_run_platform_tests(); 193 #endif 194 } 195 196 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 197 { 198 return css_scmi_override_pm_ops(ops); 199 } 200 201 void __init bl31_plat_arch_setup(void) 202 { 203 arm_bl31_plat_arch_setup(); 204 205 /* HW_CONFIG was also loaded by BL2 */ 206 const struct dyn_cfg_dtb_info_t *hw_config_info; 207 208 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 209 assert(hw_config_info != NULL); 210 211 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 212 } 213 214 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 215 void tc_bl31_plat_runtime_setup(void) 216 { 217 /* Start secure watchdog timer. */ 218 plat_arm_secure_wdt_start(); 219 220 arm_bl31_plat_runtime_setup(); 221 } 222 223 void bl31_plat_runtime_setup(void) 224 { 225 tc_bl31_plat_runtime_setup(); 226 } 227 228 /* 229 * Platform handler for Group0 secure interrupt. 230 */ 231 int plat_spmd_handle_group0_interrupt(uint32_t intid) 232 { 233 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 234 if (intid == SBSA_SECURE_WDOG_INTID) { 235 /* Refresh the timer. */ 236 plat_arm_secure_wdt_refresh(); 237 238 return 0; 239 } 240 241 return -1; 242 } 243 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 244