1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 29 #ifdef PLATFORM_TEST_TFM_TESTSUITE 30 /* 31 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 32 * mbedTLS config option) so we need to provide an implementation of 33 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 34 * actually use any of external RNG and this function is only needed during 35 * the execution of TF-M testsuite during exporting the public part of the 36 * delegated attestation key. 37 */ 38 psa_status_t mbedtls_psa_external_get_random( 39 mbedtls_psa_external_random_context_t *context, 40 uint8_t *output, size_t output_size, 41 size_t *output_length) 42 { 43 for (size_t i = 0U; i < output_size; i++) { 44 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 45 } 46 47 *output_length = output_size; 48 49 return PSA_SUCCESS; 50 } 51 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 52 53 #if TARGET_PLATFORM <= 2 54 static scmi_channel_plat_info_t tc_scmi_plat_info = { 55 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 56 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 57 .db_preserve_mask = 0xfffffffe, 58 .db_modify_mask = 0x1, 59 .ring_doorbell = &mhuv2_ring_doorbell, 60 }; 61 #elif TARGET_PLATFORM == 3 62 static scmi_channel_plat_info_t tc_scmi_plat_info = { 63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 64 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 65 .db_preserve_mask = 0xfffffffe, 66 .db_modify_mask = 0x1, 67 .ring_doorbell = &mhu_ring_doorbell, 68 }; 69 #endif 70 71 void bl31_platform_setup(void) 72 { 73 tc_bl31_common_platform_setup(); 74 } 75 76 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 77 { 78 79 return &tc_scmi_plat_info; 80 81 } 82 83 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 84 u_register_t arg2, u_register_t arg3) 85 { 86 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 87 88 /* Fill the properties struct with the info from the config dtb */ 89 fconf_populate("FW_CONFIG", arg1); 90 } 91 92 #ifdef PLATFORM_TESTS 93 static __dead2 void tc_run_platform_tests(void) 94 { 95 int tests_failed; 96 97 printf("\nStarting platform tests...\n"); 98 99 #ifdef PLATFORM_TEST_NV_COUNTERS 100 tests_failed = nv_counter_test(); 101 #elif PLATFORM_TEST_ROTPK 102 tests_failed = rotpk_test(); 103 #elif PLATFORM_TEST_TFM_TESTSUITE 104 tests_failed = run_platform_tests(); 105 #endif 106 107 printf("Platform tests %s.\n", 108 (tests_failed != 0) ? "failed" : "succeeded"); 109 110 /* Suspend booting, no matter the tests outcome. */ 111 printf("Suspend booting...\n"); 112 plat_error_handler(-1); 113 } 114 #endif 115 116 void tc_bl31_common_platform_setup(void) 117 { 118 arm_bl31_platform_setup(); 119 120 #ifdef PLATFORM_TESTS 121 tc_run_platform_tests(); 122 #endif 123 } 124 125 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 126 { 127 return css_scmi_override_pm_ops(ops); 128 } 129 130 void __init bl31_plat_arch_setup(void) 131 { 132 arm_bl31_plat_arch_setup(); 133 134 /* HW_CONFIG was also loaded by BL2 */ 135 const struct dyn_cfg_dtb_info_t *hw_config_info; 136 137 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 138 assert(hw_config_info != NULL); 139 140 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 141 } 142 143 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 144 void tc_bl31_plat_runtime_setup(void) 145 { 146 /* Start secure watchdog timer. */ 147 plat_arm_secure_wdt_start(); 148 149 arm_bl31_plat_runtime_setup(); 150 } 151 152 void bl31_plat_runtime_setup(void) 153 { 154 tc_bl31_plat_runtime_setup(); 155 } 156 157 /* 158 * Platform handler for Group0 secure interrupt. 159 */ 160 int plat_spmd_handle_group0_interrupt(uint32_t intid) 161 { 162 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 163 if (intid == SBSA_SECURE_WDOG_INTID) { 164 /* Refresh the timer. */ 165 plat_arm_secure_wdt_refresh(); 166 167 return 0; 168 } 169 170 return -1; 171 } 172 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 173