1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 #include <psa/error.h> 29 30 #include <drivers/arm/rse_comms.h> 31 #include <plat/common/platform.h> 32 33 #ifdef PLATFORM_TEST_TFM_TESTSUITE 34 /* 35 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 36 * mbedTLS config option) so we need to provide an implementation of 37 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 38 * actually use any of external RNG and this function is only needed during 39 * the execution of TF-M testsuite during exporting the public part of the 40 * delegated attestation key. 41 */ 42 psa_status_t mbedtls_psa_external_get_random( 43 mbedtls_psa_external_random_context_t *context, 44 uint8_t *output, size_t output_size, 45 size_t *output_length) 46 { 47 for (size_t i = 0U; i < output_size; i++) { 48 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 49 } 50 51 *output_length = output_size; 52 53 return PSA_SUCCESS; 54 } 55 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 56 57 #if TARGET_PLATFORM <= 2 58 static scmi_channel_plat_info_t tc_scmi_plat_info = { 59 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 60 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 61 .db_preserve_mask = 0xfffffffe, 62 .db_modify_mask = 0x1, 63 .ring_doorbell = &mhuv2_ring_doorbell, 64 }; 65 #elif TARGET_PLATFORM >= 3 66 static scmi_channel_plat_info_t tc_scmi_plat_info = { 67 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 68 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 69 .db_preserve_mask = 0xfffffffe, 70 .db_modify_mask = 0x1, 71 .ring_doorbell = &mhu_ring_doorbell, 72 }; 73 #endif 74 75 #if TARGET_PLATFORM == 3 76 static void enable_ns_mcn_pmu(void) 77 { 78 /* 79 * Enable non-secure access to MCN PMU registers 80 */ 81 for (int i = 0; i < MCN_INSTANCES; i++) { 82 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET + 83 (i * MCN_ADDRESS_SPACE_SIZE); 84 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 85 } 86 } 87 88 static void set_mcn_slc_alloc_mode(void) 89 { 90 /* 91 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 92 * 0b01 (always alloc), configure both to 0b10 (use bus signal 93 * attribute from interface). 94 */ 95 for (int i = 0; i < MCN_INSTANCES; i++) { 96 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR + 97 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 98 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR + 99 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 100 101 mmio_clrsetbits_32(slccfg_ctl_ns, 102 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 103 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 104 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 105 mmio_clrsetbits_32(slccfg_ctl_s, 106 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 107 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 108 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 109 } 110 } 111 #endif 112 113 void bl31_platform_setup(void) 114 { 115 tc_bl31_common_platform_setup(); 116 #if TARGET_PLATFORM == 3 117 enable_ns_mcn_pmu(); 118 set_mcn_slc_alloc_mode(); 119 plat_arm_ni_setup(NCI_BASE_ADDR); 120 #endif 121 } 122 123 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 124 { 125 126 return &tc_scmi_plat_info; 127 128 } 129 130 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 131 u_register_t arg2, u_register_t arg3) 132 { 133 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 134 135 /* Fill the properties struct with the info from the config dtb */ 136 fconf_populate("FW_CONFIG", arg1); 137 } 138 139 #ifdef PLATFORM_TESTS 140 static __dead2 void tc_run_platform_tests(void) 141 { 142 int tests_failed; 143 144 printf("\nStarting platform tests...\n"); 145 146 #ifdef PLATFORM_TEST_NV_COUNTERS 147 tests_failed = nv_counter_test(); 148 #elif PLATFORM_TEST_ROTPK 149 tests_failed = rotpk_test(); 150 #elif PLATFORM_TEST_TFM_TESTSUITE 151 tests_failed = run_platform_tests(); 152 #endif 153 154 printf("Platform tests %s.\n", 155 (tests_failed != 0) ? "failed" : "succeeded"); 156 157 /* Suspend booting, no matter the tests outcome. */ 158 printf("Suspend booting...\n"); 159 plat_error_handler(-1); 160 } 161 #endif 162 163 void tc_bl31_common_platform_setup(void) 164 { 165 arm_bl31_platform_setup(); 166 167 #ifdef PLATFORM_TESTS 168 tc_run_platform_tests(); 169 #endif 170 } 171 172 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 173 { 174 return css_scmi_override_pm_ops(ops); 175 } 176 177 void __init bl31_plat_arch_setup(void) 178 { 179 arm_bl31_plat_arch_setup(); 180 181 /* HW_CONFIG was also loaded by BL2 */ 182 const struct dyn_cfg_dtb_info_t *hw_config_info; 183 184 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 185 assert(hw_config_info != NULL); 186 187 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 188 } 189 190 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 191 void tc_bl31_plat_runtime_setup(void) 192 { 193 /* Start secure watchdog timer. */ 194 plat_arm_secure_wdt_start(); 195 196 arm_bl31_plat_runtime_setup(); 197 198 /* Initialise RSE communication channel */ 199 status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE); 200 if (status != PSA_SUCCESS) { 201 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status); 202 } 203 } 204 205 void bl31_plat_runtime_setup(void) 206 { 207 tc_bl31_plat_runtime_setup(); 208 } 209 210 /* 211 * Platform handler for Group0 secure interrupt. 212 */ 213 int plat_spmd_handle_group0_interrupt(uint32_t intid) 214 { 215 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 216 if (intid == SBSA_SECURE_WDOG_INTID) { 217 /* Refresh the timer. */ 218 plat_arm_secure_wdt_refresh(); 219 220 return 0; 221 } 222 223 return -1; 224 } 225 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 226