1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/sbsa.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 29 #ifdef PLATFORM_TEST_TFM_TESTSUITE 30 /* 31 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 32 * mbedTLS config option) so we need to provide an implementation of 33 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 34 * actually use any of external RNG and this function is only needed during 35 * the execution of TF-M testsuite during exporting the public part of the 36 * delegated attestation key. 37 */ 38 psa_status_t mbedtls_psa_external_get_random( 39 mbedtls_psa_external_random_context_t *context, 40 uint8_t *output, size_t output_size, 41 size_t *output_length) 42 { 43 for (size_t i = 0U; i < output_size; i++) { 44 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 45 } 46 47 *output_length = output_size; 48 49 return PSA_SUCCESS; 50 } 51 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 52 53 #if TARGET_PLATFORM <= 2 54 static scmi_channel_plat_info_t tc_scmi_plat_info = { 55 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 56 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 57 .db_preserve_mask = 0xfffffffe, 58 .db_modify_mask = 0x1, 59 .ring_doorbell = &mhuv2_ring_doorbell, 60 }; 61 #elif TARGET_PLATFORM >= 3 62 static scmi_channel_plat_info_t tc_scmi_plat_info = { 63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 64 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 65 .db_preserve_mask = 0xfffffffe, 66 .db_modify_mask = 0x1, 67 .ring_doorbell = &mhu_ring_doorbell, 68 }; 69 #endif 70 71 #if TARGET_PLATFORM == 3 72 static void enable_ns_mcn_pmu(void) 73 { 74 /* 75 * Enable non-secure access to MCN PMU registers 76 */ 77 for (int i = 0; i < MCN_INSTANCES; i++) { 78 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET + 79 (i * MCN_ADDRESS_SPACE_SIZE); 80 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 81 } 82 } 83 84 static void set_mcn_slc_alloc_mode(void) 85 { 86 /* 87 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 88 * 0b01 (always alloc), configure both to 0b10 (use bus signal 89 * attribute from interface). 90 */ 91 for (int i = 0; i < MCN_INSTANCES; i++) { 92 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR + 93 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 94 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR + 95 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; 96 97 mmio_clrsetbits_32(slccfg_ctl_ns, 98 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 99 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 100 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 101 mmio_clrsetbits_32(slccfg_ctl_s, 102 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 103 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 104 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 105 } 106 } 107 #endif 108 109 void bl31_platform_setup(void) 110 { 111 tc_bl31_common_platform_setup(); 112 #if TARGET_PLATFORM == 3 113 enable_ns_mcn_pmu(); 114 set_mcn_slc_alloc_mode(); 115 plat_arm_ni_setup(NCI_BASE_ADDR); 116 #endif 117 } 118 119 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 120 { 121 122 return &tc_scmi_plat_info; 123 124 } 125 126 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 127 u_register_t arg2, u_register_t arg3) 128 { 129 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 130 131 /* Fill the properties struct with the info from the config dtb */ 132 fconf_populate("FW_CONFIG", arg1); 133 } 134 135 #ifdef PLATFORM_TESTS 136 static __dead2 void tc_run_platform_tests(void) 137 { 138 int tests_failed; 139 140 printf("\nStarting platform tests...\n"); 141 142 #ifdef PLATFORM_TEST_NV_COUNTERS 143 tests_failed = nv_counter_test(); 144 #elif PLATFORM_TEST_ROTPK 145 tests_failed = rotpk_test(); 146 #elif PLATFORM_TEST_TFM_TESTSUITE 147 tests_failed = run_platform_tests(); 148 #endif 149 150 printf("Platform tests %s.\n", 151 (tests_failed != 0) ? "failed" : "succeeded"); 152 153 /* Suspend booting, no matter the tests outcome. */ 154 printf("Suspend booting...\n"); 155 plat_error_handler(-1); 156 } 157 #endif 158 159 void tc_bl31_common_platform_setup(void) 160 { 161 arm_bl31_platform_setup(); 162 163 #ifdef PLATFORM_TESTS 164 tc_run_platform_tests(); 165 #endif 166 } 167 168 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 169 { 170 return css_scmi_override_pm_ops(ops); 171 } 172 173 void __init bl31_plat_arch_setup(void) 174 { 175 arm_bl31_plat_arch_setup(); 176 177 /* HW_CONFIG was also loaded by BL2 */ 178 const struct dyn_cfg_dtb_info_t *hw_config_info; 179 180 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 181 assert(hw_config_info != NULL); 182 183 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 184 } 185 186 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 187 void tc_bl31_plat_runtime_setup(void) 188 { 189 /* Start secure watchdog timer. */ 190 plat_arm_secure_wdt_start(); 191 192 arm_bl31_plat_runtime_setup(); 193 } 194 195 void bl31_plat_runtime_setup(void) 196 { 197 tc_bl31_plat_runtime_setup(); 198 } 199 200 /* 201 * Platform handler for Group0 secure interrupt. 202 */ 203 int plat_spmd_handle_group0_interrupt(uint32_t intid) 204 { 205 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 206 if (intid == SBSA_SECURE_WDOG_INTID) { 207 /* Refresh the timer. */ 208 plat_arm_secure_wdt_refresh(); 209 210 return 0; 211 } 212 213 return -1; 214 } 215 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 216