1# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6RD_N2_VARIANTS := 0 1 2 3 7ifneq ($(NRD_PLATFORM_VARIANT),\ 8 $(filter $(NRD_PLATFORM_VARIANT),$(RD_N2_VARIANTS))) 9 $(error "NRD_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \ 10 set to ${NRD_PLATFORM_VARIANT}.") 11endif 12 13$(eval $(call CREATE_SEQ,SEQ,4)) 14ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ))) 15 $(error "Chip count for RD-N2-MC should be either $(SEQ) \ 16 currently it is set to ${NRD_CHIP_COUNT}.") 17endif 18 19# RD-N2 platform uses GIC-700 which is based on GICv4.1 20GIC_ENABLE_V4_EXTN := 1 21GIC_EXT_INTID := 1 22 23#Enable GIC Multichip Extension only for Multichip Platforms 24ifeq (${NRD_PLATFORM_VARIANT}, 2) 25GICV3_IMPL_GIC600_MULTICHIP := 1 26endif 27 28override CSS_SYSTEM_GRACEFUL_RESET := 1 29override EL3_EXCEPTION_HANDLING := 1 30 31include plat/arm/board/neoverse_rd/common/nrd-common.mk 32 33RDN2_BASE = plat/arm/board/neoverse_rd/platform/rdn2 34 35PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd2/ \ 36 -I${RDN2_BASE}/include/ 37 38NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \ 39 lib/cpus/aarch64/neoverse_v2.S 40 41PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat2.c 42 43BL1_SOURCES += ${NRD_CPU_SOURCES} \ 44 ${RDN2_BASE}/rdn2_err.c 45 46BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \ 47 ${RDN2_BASE}/rdn2_security.c \ 48 ${RDN2_BASE}/rdn2_err.c \ 49 lib/utils/mem_region.c \ 50 drivers/arm/tzc/tzc400.c \ 51 plat/arm/common/arm_tzc400.c \ 52 plat/arm/common/arm_nor_psci_mem_protect.c 53 54BL31_SOURCES += ${NRD_CPU_SOURCES} \ 55 ${RDN2_BASE}/rdn2_plat.c \ 56 ${RDN2_BASE}/rdn2_topology.c \ 57 drivers/cfi/v2m/v2m_flash.c \ 58 lib/utils/mem_region.c \ 59 plat/arm/common/arm_nor_psci_mem_protect.c 60 61ifeq (${TRUSTED_BOARD_BOOT}, 1) 62BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c 63BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c 64endif 65 66ifeq (${NRD_PLATFORM_VARIANT}, 2) 67BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c 68 69# Enable dynamic addition of MMAP regions in BL31 70BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 71endif 72 73ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 74BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \ 75 ${NRD_COMMON_BASE}/ras/nrd_ras_common.c \ 76 ${NRD_COMMON_BASE}/ras/nrd_ras_sram.c \ 77 ${NRD_COMMON_BASE}/ras/nrd_ras_cpu.c 78endif 79 80# Add the FDT_SOURCES and options for Dynamic Config 81FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \ 82 ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts 83FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 84TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 85 86# Add the FW_CONFIG to FIP and specify the same to certtool 87$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 88# Add the TB_FW_CONFIG to FIP and specify the same to certtool 89$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 90 91FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts 92NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 93 94# Add the NT_FW_CONFIG to FIP and specify the same to certtool 95$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) 96 97ifeq (${SPMC_AT_EL3}, 1) 98STMM_CONFIG_DTS := ${RDN2_BASE}/fdts/${PLAT}_stmm_sel0_manifest.dts 99FDT_SOURCES += ${STMM_CONFIG_DTS} 100TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${STMM_CONFIG_DTS})).dtb 101 102# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 103$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG})) 104endif 105 106ifneq (${RESET_TO_BL31},0) 107 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 108 Please set RESET_TO_BL31 to 0.") 109endif 110 111override CTX_INCLUDE_AARCH32_REGS := 0 112override ENABLE_FEAT_AMU := 2 113override ENABLE_FEAT_MTE2 := 2 114override SPMD_SPM_AT_SEL2 := 0 115 116# FEAT_SVE related flags 117override SVE_VECTOR_LEN := 128 118# Enable the flag since RD-N2 has a system level cache 119NEOVERSE_Nx_EXTERNAL_LLC := 1 120 121# Enable N2 CPU errata workarounds 122ERRATA_N2_2002655 := 1 123ERRATA_N2_2009478 := 1 124ERRATA_N2_2067956 := 1 125ERRATA_N2_2025414 := 1 126ERRATA_N2_2189731 := 1 127ERRATA_N2_2138956 := 1 128ERRATA_N2_2242415 := 1 129ERRATA_N2_2138958 := 1 130ERRATA_N2_2242400 := 1 131ERRATA_N2_2280757 := 1 132ERRATA_N2_2326639 := 1 133ERRATA_N2_2340933 := 1 134ERRATA_N2_2346952 := 1 135ERRATA_N2_2376738 := 1 136ERRATA_N2_2388450 := 1 137ERRATA_N2_2743014 := 1 138ERRATA_N2_2743089 := 1 139ERRATA_N2_2728475 := 1 140ERRATA_N2_2779511 := 1 141