Merge "feat(neoverse-rd): set the correct Arm version for rdn2" into integration

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I1

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I15556fde3740056b1eb81138d19635b507064abf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix: remove circular dependency on ENABLE_FEAT_RAS" into integration

fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platfor

fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platform.mk. That makes a circular dependency when a file needs to be
compiled based on the flag's value.

Well, FEAT_RAS is mandatory from v8.2 and platforms that set
ARM_ARCH_{MAJOR, MINOR} such need not check for its presence - it will
be present. So remove the check to remove the dependency.

Change-Id: I68db83347e6bc04b7ff3b67f6c3e54921641db23
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): remove errata setting PF_MODE to conservative" into integration

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths

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fix(neoverse-rd): set correct SVE vector lengths

Affected platforms: RD-N2, RD-V1, RD-V1-MC, RD-V3 and their
configurations.

Previously, the SVE vector lengths for these platforms were
being taken

fix(neoverse-rd): set correct SVE vector lengths

Affected platforms: RD-N2, RD-V1, RD-V1-MC, RD-V3 and their
configurations.

Previously, the SVE vector lengths for these platforms were
being taken from the default configuration. This commit updates
their respective platform.mk files to specify the correct vector
lengths.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8919257e2cec5c0e819424ff44a623dc3ab1a368

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Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow
feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3
feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

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feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subra

feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I30256969e5671043b3e58c76922985f7252429af

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Merge changes from topic "nrd2_refactor" into integration

* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(n

Merge changes from topic "nrd2_refactor" into integration

* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(neoverse-rd): unify GIC SPI range macros
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
feat(rdn2): enable AMU if present on the platform
feat(rdn2): enable MTE2 if present on the platform
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
refactor(neoverse-rd): define naming convention for RoS macros
refactor(neoverse-rd): define naming convention for CSS macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): set mmap naming convention
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
refactor(neoverse-rd): refactor nrd_base_platform_def.h
refactor(neoverse-rd): header files for second generation platforms

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feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value t

feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7

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feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could a

feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e

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feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
c

feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d

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refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention

Header files for N2 CPU based platforms currently use "2" as
a suffix. Rename the common source file, nrd_plat_v2.c used by these

refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention

Header files for N2 CPU based platforms currently use "2" as
a suffix. Rename the common source file, nrd_plat_v2.c used by these
platforms to nrd_plat2.c to align with this convention.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I36b138a0a4dff8087e52f0f2cbc21abc03a793ad

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refactor(neoverse-rd): header files for second generation platforms

Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2
utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h fo

refactor(neoverse-rd): header files for second generation platforms

Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2
utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h for all css
and soc-related defines. So move these two header files into a new
directory named 'nrd2'. This new directory will serve as the container
of header files that are specific to the former stated platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I51ba0944dea91ae81e1840947d2e9af9b28d561d

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Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refa

Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refactor(sgi): move apis and types to "nrd" prefix
refactor(sgi): replace build-option prefix to "NRD"
refactor(sgi): move neoverse_rd out of css
refactor(sgi): move from "sgi" to "neoverse_rd"
feat(sgi): remove unused SGI_PLAT build-option
fix(sgi): align to misra rule for braces
feat(rde1edge): remove support for RD-E1-Edge
fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
fix(board): update spi_id max for sgi multichip platforms

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refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of

refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of the
migration to neoverse_rd, rename all occurences of "SGI/sgi" to
"Neoverse-RD" or the "NRD" prefix accordingly. All references in
comments are rephrased as "Neoverse RD platforms". References in code
are renamed as "NRD"/"nrd" accordingly.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iec195427ff2bee565cb4a325a1a22892be95ae16

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refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed t

refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed to "neoverse_rd" and the source files have been migrated out of
the css directory, replace the prefix "CSS_SGI" with "NRD".

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I27989ff42404d823dd2a8cd22ff485497ccb62d4

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refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources

refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources. Since neoverse_rd hosts source and header for css
and soc, move neoverse_rd from css to board folder. Consolidate common
sources and headers under neoverse_rd/common. Additionally, group RD-V1,
RD-V1-MC, RD-N2, RD-N1-Edgex2 and SGI-575 within neoverse_rd/platform.
With the changes in this commit, the tree view would look as follows:

plat/arm/board/neoverse_rd/
├── common
│   ├── arch
│   ├── include
│   └── ras
└── platform
├── rdn1edge
├── rdn2
├── rdv1
├── rdv1mc
└── sgi575

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iaccc86bc9d415f5c045c834902241fcf3c00277b

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