1 /*
2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <drivers/arm/css/sds.h>
10 #include <drivers/arm/sbsa.h>
11 #include <lib/utils_def.h>
12 #include <plat/arm/common/plat_arm.h>
13 #include <plat/common/platform.h>
14
15 #include <platform_def.h>
16
17 /*
18 * Table of regions for different BL stages to map using the MMU.
19 */
20 #if IMAGE_BL1
21 const mmap_region_t plat_arm_mmap[] = {
22 NRD_CSS_SHARED_RAM_MMAP(0),
23 NRD_ROS_FLASH0_RO_MMAP,
24 NRD_CSS_PERIPH_MMAP(0),
25 NRD_ROS_PLATFORM_PERIPH_MMAP,
26 NRD_ROS_SYSTEM_PERIPH_MMAP,
27 {0}
28 };
29 #endif /* IMAGE_BL3 */
30
31 #if IMAGE_BL2
32 const mmap_region_t plat_arm_mmap[] = {
33 NRD_CSS_SHARED_RAM_MMAP(0),
34 NRD_ROS_FLASH0_RO_MMAP,
35 #ifdef PLAT_ARM_MEM_PROT_ADDR
36 NRD_ROS_V2M_MEM_PROTECT_MMAP,
37 #endif
38 NRD_CSS_PERIPH_MMAP(0),
39 NRD_ROS_PLATFORM_PERIPH_MMAP,
40 NRD_ROS_SYSTEM_PERIPH_MMAP,
41 NRD_CSS_NS_DRAM1_MMAP,
42 #if SPD_spmd && SPMD_SPM_AT_SEL2
43 NRD_CSS_SPM_CORE_REGION_MMAP,
44 #endif
45 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
46 NRD_CSS_BL1_RW_MMAP,
47 #endif
48 NRD_CSS_GPT_L1_DRAM_MMAP,
49 NRD_CSS_RMM_REGION_MMAP,
50 {0}
51 };
52 #endif /* IMAGE_BL2 */
53
54 #if IMAGE_BL31
55 const mmap_region_t plat_arm_mmap[] = {
56 NRD_CSS_SHARED_RAM_MMAP(0),
57 #ifdef PLAT_ARM_MEM_PROT_ADDR
58 NRD_ROS_V2M_MEM_PROTECT_MMAP,
59 #endif
60 NRD_CSS_PERIPH_MMAP(0),
61 NRD_ROS_PLATFORM_PERIPH_MMAP,
62 NRD_ROS_SYSTEM_PERIPH_MMAP,
63 NRD_CSS_GPT_L1_DRAM_MMAP,
64 NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
65 NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
66 #if RESET_TO_BL31
67 NRD_CSS_MAP_BL31_DTB,
68 #endif
69 {0}
70 };
71 #endif /* IMAGE_BL31 */
72
73 ARM_CASSERT_MMAP
74
75 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)76 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
77 {
78 assert(heap_addr != NULL);
79 assert(heap_size != NULL);
80
81 return arm_get_mbedtls_heap(heap_addr, heap_size);
82 }
83 #endif
84
plat_arm_secure_wdt_start(void)85 void plat_arm_secure_wdt_start(void)
86 {
87 sbsa_wdog_start(NRD_CSS_AP_SECURE_WDOG_BASE,
88 NRD_CSS_AP_SECURE_WDOG_TIMEOUT);
89 }
90
plat_arm_secure_wdt_stop(void)91 void plat_arm_secure_wdt_stop(void)
92 {
93 sbsa_wdog_stop(NRD_CSS_AP_SECURE_WDOG_BASE);
94 }
95
96 static sds_region_desc_t nrd_sds_regions[] = {
97 { .base = PLAT_ARM_SDS_MEM_BASE },
98 };
99
plat_sds_get_regions(unsigned int * region_count)100 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
101 {
102 *region_count = ARRAY_SIZE(nrd_sds_regions);
103
104 return nrd_sds_regions;
105 }
106