1# 2# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Use the SP804 timer instead of the generic one 11FVP_USE_SP804_TIMER := 0 12 13# Default cluster count for FVP 14FVP_CLUSTER_COUNT := 2 15 16# Default number of CPUs per cluster on FVP 17FVP_MAX_CPUS_PER_CLUSTER := 4 18 19# Default number of threads per CPU on FVP 20FVP_MAX_PE_PER_CPU := 1 21 22FVP_DT_PREFIX := fvp-base-gicv3-psci 23 24$(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) 25$(eval $(call add_define,FVP_USE_SP804_TIMER)) 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 40# choose the CCI driver , else the CCN driver 41ifeq ($(FVP_CLUSTER_COUNT), 0) 42$(error "Incorrect cluster count specified for FVP port") 43else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 44FVP_INTERCONNECT_DRIVER := FVP_CCI 45else 46FVP_INTERCONNECT_DRIVER := FVP_CCN 47endif 48 49$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 50 51FVP_GICV3_SOURCES := drivers/arm/gic/common/gic_common.c \ 52 drivers/arm/gic/v3/gicv3_main.c \ 53 drivers/arm/gic/v3/gicv3_helpers.c \ 54 plat/common/plat_gicv3.c \ 55 plat/arm/common/arm_gicv3.c 56 57# Choose the GIC sources depending upon the how the FVP will be invoked 58ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 59FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \ 60 drivers/arm/gic/v3/gic500.c 61else ifeq (${FVP_USE_GIC_DRIVER},FVP_GIC600) 62FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \ 63 drivers/arm/gic/v3/gic600.c 64else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 65FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 66 drivers/arm/gic/v2/gicv2_main.c \ 67 drivers/arm/gic/v2/gicv2_helpers.c \ 68 plat/common/plat_gicv2.c \ 69 plat/arm/common/arm_gicv2.c 70 71FVP_DT_PREFIX := fvp-base-gicv2-psci 72else 73$(error "Incorrect GIC driver chosen on FVP port") 74endif 75 76ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 77FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 78else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 79FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 80 plat/arm/common/arm_ccn.c 81else 82$(error "Incorrect CCN driver chosen on FVP port") 83endif 84 85FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 86 plat/arm/board/fvp/fvp_security.c \ 87 plat/arm/common/arm_tzc400.c 88 89 90PLAT_INCLUDES := -Iplat/arm/board/fvp/include 91 92 93PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 94 95FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 96 97ifeq (${ARCH}, aarch64) 98 99# select a different set of CPU files, depending on whether we compile for 100# hardware assisted coherency cores or not 101ifeq (${HW_ASSISTED_COHERENCY}, 0) 102 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 103 lib/cpus/aarch64/cortex_a53.S \ 104 lib/cpus/aarch64/cortex_a57.S \ 105 lib/cpus/aarch64/cortex_a72.S \ 106 lib/cpus/aarch64/cortex_a73.S 107else 108 # AArch64-only cores 109 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 110 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 111 lib/cpus/aarch64/cortex_a76ae.S \ 112 lib/cpus/aarch64/cortex_a77.S \ 113 lib/cpus/aarch64/neoverse_n1.S \ 114 lib/cpus/aarch64/neoverse_e1.S \ 115 lib/cpus/aarch64/neoverse_zeus.S \ 116 lib/cpus/aarch64/cortex_hercules.S 117 # AArch64/AArch32 118 else 119 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 120 lib/cpus/aarch64/cortex_a75.S 121 endif 122endif 123 124else 125FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 126endif 127 128BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 129 drivers/arm/sp805/sp805.c \ 130 drivers/delay_timer/delay_timer.c \ 131 drivers/io/io_semihosting.c \ 132 lib/semihosting/semihosting.c \ 133 lib/semihosting/${ARCH}/semihosting_call.S \ 134 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 135 plat/arm/board/fvp/fvp_bl1_setup.c \ 136 plat/arm/board/fvp/fvp_err.c \ 137 plat/arm/board/fvp/fvp_io_storage.c \ 138 plat/arm/board/fvp/fvp_trusted_boot.c \ 139 ${FVP_CPU_LIBS} \ 140 ${FVP_INTERCONNECT_SOURCES} 141 142ifeq (${FVP_USE_SP804_TIMER},1) 143BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 144else 145BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 146endif 147 148 149BL2_SOURCES += drivers/arm/sp805/sp805.c \ 150 drivers/io/io_semihosting.c \ 151 lib/utils/mem_region.c \ 152 lib/semihosting/semihosting.c \ 153 lib/semihosting/${ARCH}/semihosting_call.S \ 154 plat/arm/board/fvp/fvp_bl2_setup.c \ 155 plat/arm/board/fvp/fvp_err.c \ 156 plat/arm/board/fvp/fvp_io_storage.c \ 157 plat/arm/board/fvp/fvp_trusted_boot.c \ 158 plat/arm/common/arm_nor_psci_mem_protect.c \ 159 ${FVP_SECURITY_SOURCES} 160 161 162 163ifeq (${BL2_AT_EL3},1) 164BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 165 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 166 ${FVP_CPU_LIBS} \ 167 ${FVP_INTERCONNECT_SOURCES} 168endif 169 170ifeq (${FVP_USE_SP804_TIMER},1) 171BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 172endif 173 174BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 175 ${FVP_SECURITY_SOURCES} 176 177ifeq (${FVP_USE_SP804_TIMER},1) 178BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 179endif 180 181BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 182 drivers/arm/smmu/smmu_v3.c \ 183 drivers/delay_timer/delay_timer.c \ 184 drivers/cfi/v2m/v2m_flash.c \ 185 lib/utils/mem_region.c \ 186 plat/arm/board/fvp/fvp_bl31_setup.c \ 187 plat/arm/board/fvp/fvp_pm.c \ 188 plat/arm/board/fvp/fvp_topology.c \ 189 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 190 plat/arm/common/arm_nor_psci_mem_protect.c \ 191 ${FVP_CPU_LIBS} \ 192 ${FVP_GIC_SOURCES} \ 193 ${FVP_INTERCONNECT_SOURCES} \ 194 ${FVP_SECURITY_SOURCES} 195 196ifeq (${FVP_USE_SP804_TIMER},1) 197BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 198else 199BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 200endif 201 202# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 203ifdef UNIX_MK 204FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 205FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 206 ${PLAT}_tb_fw_config.dts \ 207 ${PLAT}_soc_fw_config.dts \ 208 ${PLAT}_nt_fw_config.dts \ 209 ) 210 211FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 212FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 213FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 214 215ifeq (${SPD},tspd) 216FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 217FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 218 219# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 220$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 221endif 222 223# Add the TB_FW_CONFIG to FIP and specify the same to certtool 224$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) 225# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 226$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config)) 227# Add the NT_FW_CONFIG to FIP and specify the same to certtool 228$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config)) 229 230FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 231$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 232 233# Add the HW_CONFIG to FIP and specify the same to certtool 234$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) 235endif 236 237# Enable Activity Monitor Unit extensions by default 238ENABLE_AMU := 1 239 240# Enable dynamic mitigation support by default 241DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 242 243ifneq (${RESET_TO_BL31},1) 244# Enable reclaiming of BL31 initialisation code for secondary cores stacks for 245# FVP. We cannot enable PIE for this case because the overlayed init section 246# creates some dynamic relocations which cannot be handled by the fixup 247# logic currently. 248RECLAIM_INIT_CODE := 1 249else 250# Enable PIE support when RESET_TO_BL31=1 251ENABLE_PIE := 1 252endif 253 254ifeq (${ENABLE_AMU},1) 255BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 256 lib/cpus/aarch64/cpuamu_helpers.S 257 258ifeq (${HW_ASSISTED_COHERENCY}, 1) 259BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 260 lib/cpus/aarch64/neoverse_n1_pubsub.c 261endif 262endif 263 264ifeq (${RAS_EXTENSION},1) 265BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 266endif 267 268ifneq (${ENABLE_STACK_PROTECTOR},0) 269PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 270endif 271 272ifeq (${ARCH},aarch32) 273 NEED_BL32 := yes 274endif 275 276# Enable the dynamic translation tables library. 277ifeq (${ARCH},aarch32) 278 ifeq (${RESET_TO_SP_MIN},1) 279 BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 280 endif 281else # if AArch64 282 ifeq (${RESET_TO_BL31},1) 283 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 284 endif 285 ifeq (${ENABLE_SPM},1) 286 ifeq (${SPM_MM},0) 287 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 288 endif 289 endif 290 ifeq (${SPD},trusty) 291 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 292 endif 293endif 294 295# Add support for platform supplied linker script for BL31 build 296$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 297 298ifneq (${BL2_AT_EL3}, 0) 299 override BL1_SOURCES = 300endif 301 302include plat/arm/board/common/board_common.mk 303include plat/arm/common/arm_common.mk 304 305# FVP being a development platform, enable capability to disable Authentication 306# dynamically if TRUSTED_BOARD_BOOT is set. 307ifeq (${TRUSTED_BOARD_BOOT}, 1) 308 DYN_DISABLE_AUTH := 1 309endif 310