1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59endif 60 61ENABLE_SYS_REG_TRACE_FOR_NS := 2 62ENABLE_FEAT_CSV2_2 := 2 63ENABLE_FEAT_CSV2_3 := 2 64ENABLE_FEAT_DEBUGV8P9 := 2 65ENABLE_FEAT_DIT := 2 66ENABLE_FEAT_PAN := 2 67ENABLE_FEAT_VHE := 2 68CTX_INCLUDE_NEVE_REGS := 2 69ENABLE_FEAT_SEL2 := 2 70ENABLE_TRF_FOR_NS := 2 71ENABLE_FEAT_ECV := 2 72ENABLE_FEAT_FGT := 2 73ENABLE_FEAT_FGT2 := 2 74ENABLE_FEAT_THE := 2 75ENABLE_FEAT_TCR2 := 2 76ENABLE_FEAT_S2PIE := 2 77ENABLE_FEAT_S1PIE := 2 78ENABLE_FEAT_S2POE := 2 79ENABLE_FEAT_S1POE := 2 80ENABLE_FEAT_SCTLR2 := 2 81ENABLE_FEAT_MTE2 := 2 82 83# The FVP platform depends on this macro to build with correct GIC driver. 84$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 85 86# Pass FVP_CLUSTER_COUNT to the build system. 87$(eval $(call add_define,FVP_CLUSTER_COUNT)) 88 89# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 90$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 91 92# Pass FVP_MAX_PE_PER_CPU to the build system. 93$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 94 95# Pass FVP_GICR_REGION_PROTECTION to the build system. 96$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 97 98# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 99$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 100 101# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 102# choose the CCI driver , else the CCN driver 103ifeq ($(FVP_CLUSTER_COUNT), 0) 104$(error "Incorrect cluster count specified for FVP port") 105else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 106FVP_INTERCONNECT_DRIVER := FVP_CCI 107else 108FVP_INTERCONNECT_DRIVER := FVP_CCN 109endif 110 111$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 112 113# Choose the GIC sources depending upon the how the FVP will be invoked 114ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 115 116# The GIC model (GIC-600 or GIC-500) will be detected at runtime 117GICV3_SUPPORT_GIC600 := 1 118GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 119 120# Include GICv3 driver files 121include drivers/arm/gic/v3/gicv3.mk 122 123FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 124 plat/common/plat_gicv3.c \ 125 plat/arm/common/arm_gicv3.c 126 127 ifeq ($(filter 1,${RESET_TO_BL2} \ 128 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 129 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 130 endif 131 132else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 133 134# No GICv4 extension 135GIC_ENABLE_V4_EXTN := 0 136$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 137 138# Include GICv2 driver files 139include drivers/arm/gic/v2/gicv2.mk 140 141FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 142 plat/common/plat_gicv2.c \ 143 plat/arm/common/arm_gicv2.c 144 145FVP_DT_PREFIX := fvp-base-gicv2-psci 146else 147$(error "Incorrect GIC driver chosen on FVP port") 148endif 149 150ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 151FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 152else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 153FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 154 plat/arm/common/arm_ccn.c 155else 156$(error "Incorrect CCN driver chosen on FVP port") 157endif 158 159FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 160 plat/arm/board/fvp/fvp_security.c \ 161 plat/arm/common/arm_tzc400.c 162 163 164PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 165 -Iinclude/lib/psa 166 167 168PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 169 170FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 171 172ifeq (${ARCH}, aarch64) 173 174# select a different set of CPU files, depending on whether we compile for 175# hardware assisted coherency cores or not 176ifeq (${HW_ASSISTED_COHERENCY}, 0) 177# Cores used without DSU 178 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 179 lib/cpus/aarch64/cortex_a53.S \ 180 lib/cpus/aarch64/cortex_a57.S \ 181 lib/cpus/aarch64/cortex_a72.S \ 182 lib/cpus/aarch64/cortex_a73.S 183else 184# Cores used with DSU only 185 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 186 # AArch64-only cores 187 # TODO: add all cores to the appropriate lists 188 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 189 lib/cpus/aarch64/cortex_a65ae.S \ 190 lib/cpus/aarch64/cortex_a76.S \ 191 lib/cpus/aarch64/cortex_a76ae.S \ 192 lib/cpus/aarch64/cortex_a77.S \ 193 lib/cpus/aarch64/cortex_a78.S \ 194 lib/cpus/aarch64/cortex_a78_ae.S \ 195 lib/cpus/aarch64/cortex_a78c.S \ 196 lib/cpus/aarch64/cortex_a710.S \ 197 lib/cpus/aarch64/cortex_a715.S \ 198 lib/cpus/aarch64/cortex_a720.S \ 199 lib/cpus/aarch64/neoverse_n_common.S \ 200 lib/cpus/aarch64/neoverse_n1.S \ 201 lib/cpus/aarch64/neoverse_n2.S \ 202 lib/cpus/aarch64/neoverse_v1.S \ 203 lib/cpus/aarch64/neoverse_e1.S \ 204 lib/cpus/aarch64/cortex_x2.S \ 205 lib/cpus/aarch64/cortex_x4.S 206 endif 207 # AArch64/AArch32 cores 208 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 209 lib/cpus/aarch64/cortex_a75.S 210endif 211 212#Build AArch64-only CPUs with no FVP model yet. 213ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 214 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 215 lib/cpus/aarch64/cortex_gelas.S \ 216 lib/cpus/aarch64/nevis.S \ 217 lib/cpus/aarch64/travis.S \ 218 lib/cpus/aarch64/cortex_arcadia.S 219endif 220 221else 222FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 223 lib/cpus/aarch32/cortex_a57.S \ 224 lib/cpus/aarch32/cortex_a53.S 225endif 226 227BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 228 drivers/arm/sp805/sp805.c \ 229 drivers/delay_timer/delay_timer.c \ 230 drivers/io/io_semihosting.c \ 231 lib/semihosting/semihosting.c \ 232 lib/semihosting/${ARCH}/semihosting_call.S \ 233 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 234 plat/arm/board/fvp/fvp_bl1_setup.c \ 235 plat/arm/board/fvp/fvp_cpu_pwr.c \ 236 plat/arm/board/fvp/fvp_err.c \ 237 plat/arm/board/fvp/fvp_io_storage.c \ 238 plat/arm/board/fvp/fvp_topology.c \ 239 ${FVP_CPU_LIBS} \ 240 ${FVP_INTERCONNECT_SOURCES} 241 242ifeq (${USE_SP804_TIMER},1) 243BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 244else 245BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 246endif 247 248 249BL2_SOURCES += drivers/arm/sp805/sp805.c \ 250 drivers/io/io_semihosting.c \ 251 lib/utils/mem_region.c \ 252 lib/semihosting/semihosting.c \ 253 lib/semihosting/${ARCH}/semihosting_call.S \ 254 plat/arm/board/fvp/fvp_bl2_setup.c \ 255 plat/arm/board/fvp/fvp_err.c \ 256 plat/arm/board/fvp/fvp_io_storage.c \ 257 plat/arm/common/arm_nor_psci_mem_protect.c \ 258 ${FVP_SECURITY_SOURCES} 259 260 261ifeq (${COT_DESC_IN_DTB},1) 262BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 263endif 264 265ifeq (${ENABLE_RME},1) 266BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 267 plat/arm/board/fvp/fvp_cpu_pwr.c 268 269BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 270 plat/arm/board/fvp/fvp_realm_attest_key.c \ 271 plat/arm/board/fvp/fvp_el3_token_sign.c 272endif 273 274ifeq (${ENABLE_FEAT_RNG_TRAP},1) 275BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 276endif 277 278ifeq (${RESET_TO_BL2},1) 279BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 280 plat/arm/board/fvp/fvp_cpu_pwr.c \ 281 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 282 ${FVP_CPU_LIBS} \ 283 ${FVP_INTERCONNECT_SOURCES} 284endif 285 286ifeq (${USE_SP804_TIMER},1) 287BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 288endif 289 290BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 291 ${FVP_SECURITY_SOURCES} 292 293ifeq (${USE_SP804_TIMER},1) 294BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 295endif 296 297BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 298 drivers/arm/smmu/smmu_v3.c \ 299 drivers/delay_timer/delay_timer.c \ 300 drivers/cfi/v2m/v2m_flash.c \ 301 lib/utils/mem_region.c \ 302 plat/arm/board/fvp/fvp_bl31_setup.c \ 303 plat/arm/board/fvp/fvp_console.c \ 304 plat/arm/board/fvp/fvp_pm.c \ 305 plat/arm/board/fvp/fvp_topology.c \ 306 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 307 plat/arm/board/fvp/fvp_cpu_pwr.c \ 308 plat/arm/common/arm_nor_psci_mem_protect.c \ 309 ${FVP_CPU_LIBS} \ 310 ${FVP_GIC_SOURCES} \ 311 ${FVP_INTERCONNECT_SOURCES} \ 312 ${FVP_SECURITY_SOURCES} 313 314# Support for fconf in BL31 315# Added separately from the above list for better readability 316ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 317BL31_SOURCES += lib/fconf/fconf.c \ 318 lib/fconf/fconf_dyn_cfg_getter.c \ 319 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 320 321BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 322 323ifeq (${SEC_INT_DESC_IN_FCONF},1) 324BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 325endif 326 327endif 328 329ifeq (${USE_SP804_TIMER},1) 330BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 331else 332BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 333endif 334 335# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 336ifdef UNIX_MK 337FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 338FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 339 340FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 341$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 342 343ifeq (${TRANSFER_LIST}, 1) 344FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 345 ${PLAT}_tb_fw_config.dts \ 346 ) 347else 348FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 349 ${PLAT}_fw_config.dts \ 350 ${PLAT}_tb_fw_config.dts \ 351 ${PLAT}_soc_fw_config.dts \ 352 ${PLAT}_nt_fw_config.dts \ 353 ) 354 355FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 356FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 357FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 358 359ifeq (${SPD},tspd) 360FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 361FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 362 363# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 364$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 365endif 366 367ifeq (${SPD},spmd) 368 369ifeq ($(ARM_SPMC_MANIFEST_DTS),) 370ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 371endif 372 373FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 374FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 375 376# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 378endif 379 380# Add the FW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 382# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 384# Add the NT_FW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 386endif 387 388# Add the TB_FW_CONFIG to FIP and specify the same to certtool 389$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 390# Add the HW_CONFIG to FIP and specify the same to certtool 391$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 392endif 393 394ifeq (${TRANSFER_LIST}, 1) 395include lib/transfer_list/transfer_list.mk 396 397ifeq ($(RESET_TO_BL31), 1) 398HW_CONFIG := ${FVP_HW_CONFIG} 399FW_HANDOFF_SIZE := 20000 400 401TRANSFER_LIST_DTB_OFFSET := 0x20 402$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 403endif 404endif 405 406# Enable dynamic mitigation support by default 407DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 408 409ifneq (${ENABLE_FEAT_AMU},0) 410BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 411 lib/cpus/aarch64/cpuamu_helpers.S 412 413ifeq (${HW_ASSISTED_COHERENCY}, 1) 414BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 415 lib/cpus/aarch64/neoverse_n1_pubsub.c 416endif 417endif 418 419ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 420 ifeq (${ENABLE_FEAT_RAS},1) 421 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 422 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 423 else 424 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 425 endif 426 else 427 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 428 endif 429endif 430 431ifneq (${ENABLE_STACK_PROTECTOR},0) 432PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 433endif 434 435# Enable the dynamic translation tables library. 436ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 437 ifeq (${ARCH},aarch32) 438 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 439 else # AArch64 440 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 441 endif 442endif 443 444ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 445 ifeq (${ARCH},aarch32) 446 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 447 else # AArch64 448 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 449 ifeq (${SPD},tspd) 450 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 451 endif 452 endif 453endif 454 455ifeq (${USE_DEBUGFS},1) 456 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 457endif 458 459# Add support for platform supplied linker script for BL31 build 460$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 461 462ifneq (${RESET_TO_BL2}, 0) 463 override BL1_SOURCES = 464endif 465 466include plat/arm/board/common/board_common.mk 467include plat/arm/common/arm_common.mk 468 469ifeq (${MEASURED_BOOT},1) 470BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 471 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 472 lib/psa/measured_boot.c 473 474BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 475 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 476 lib/psa/measured_boot.c 477endif 478 479ifeq (${DRTM_SUPPORT}, 1) 480BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 481 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 482 plat/arm/board/fvp/fvp_drtm_err.c \ 483 plat/arm/board/fvp/fvp_drtm_measurement.c \ 484 plat/arm/board/fvp/fvp_drtm_stub.c \ 485 plat/arm/common/arm_dyn_cfg.c \ 486 plat/arm/board/fvp/fvp_err.c 487endif 488 489ifeq (${TRUSTED_BOARD_BOOT}, 1) 490BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 491BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 492 493# FVP being a development platform, enable capability to disable Authentication 494# dynamically if TRUSTED_BOARD_BOOT is set. 495DYN_DISABLE_AUTH := 1 496endif 497 498ifeq (${SPMC_AT_EL3}, 1) 499PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 500endif 501 502PSCI_OS_INIT_MODE := 1 503 504ifeq (${SPD},spmd) 505BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 506endif 507 508# Test specific macros, keep them at bottom of this file 509$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 510ifeq (${PLATFORM_TEST_EA_FFH}, 1) 511 ifeq (${FFH_SUPPORT}, 0) 512 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 513 endif 514 515endif 516 517$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 518ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 519 ifeq (${ENABLE_FEAT_RAS}, 0) 520 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 521 endif 522 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 523 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 524 endif 525endif 526 527$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 528ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 529 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 530 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 531 endif 532 ifeq (${ENABLE_SPMD_LP}, 0) 533 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 534 endif 535 ifeq (${ENABLE_FEAT_RAS}, 0) 536 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 537 endif 538 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 539 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 540 endif 541endif 542 543ifeq (${ERRATA_ABI_SUPPORT}, 1) 544include plat/arm/board/fvp/fvp_cpu_errata.mk 545endif 546 547# Build macro necessary for running SPM tests on FVP platform 548$(eval $(call add_define,PLAT_TEST_SPM)) 549