1# 2# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Default cluster count for FVP 11FVP_CLUSTER_COUNT := 2 12 13# Default number of CPUs per cluster on FVP 14FVP_MAX_CPUS_PER_CLUSTER := 4 15 16# Default number of threads per CPU on FVP 17FVP_MAX_PE_PER_CPU := 1 18 19# Disable redistributor frame of inactive/fused CPU cores by marking it as read 20# only; enable redistributor frames of all CPU cores by default. 21FVP_GICR_REGION_PROTECTION := 0 22 23FVP_DT_PREFIX := fvp-base-gicv3-psci 24 25# The FVP platform depends on this macro to build with correct GIC driver. 26$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 27 28# Pass FVP_CLUSTER_COUNT to the build system. 29$(eval $(call add_define,FVP_CLUSTER_COUNT)) 30 31# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 32$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 33 34# Pass FVP_MAX_PE_PER_CPU to the build system. 35$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 36 37# Pass FVP_GICR_REGION_PROTECTION to the build system. 38$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 39 40# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 41# choose the CCI driver , else the CCN driver 42ifeq ($(FVP_CLUSTER_COUNT), 0) 43$(error "Incorrect cluster count specified for FVP port") 44else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 45FVP_INTERCONNECT_DRIVER := FVP_CCI 46else 47FVP_INTERCONNECT_DRIVER := FVP_CCN 48endif 49 50$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 51 52# Choose the GIC sources depending upon the how the FVP will be invoked 53ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 54 55# The GIC model (GIC-600 or GIC-500) will be detected at runtime 56GICV3_SUPPORT_GIC600 := 1 57GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 58 59# Include GICv3 driver files 60include drivers/arm/gic/v3/gicv3.mk 61 62FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 63 plat/common/plat_gicv3.c \ 64 plat/arm/common/arm_gicv3.c 65 66 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 67 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 68 endif 69 70else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 71 72# No GICv4 extension 73GIC_ENABLE_V4_EXTN := 0 74$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 75 76# Include GICv2 driver files 77include drivers/arm/gic/v2/gicv2.mk 78 79FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 80 plat/common/plat_gicv2.c \ 81 plat/arm/common/arm_gicv2.c 82 83FVP_DT_PREFIX := fvp-base-gicv2-psci 84else 85$(error "Incorrect GIC driver chosen on FVP port") 86endif 87 88ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 89FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 90else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 91FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 92 plat/arm/common/arm_ccn.c 93else 94$(error "Incorrect CCN driver chosen on FVP port") 95endif 96 97FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 98 plat/arm/board/fvp/fvp_security.c \ 99 plat/arm/common/arm_tzc400.c 100 101 102PLAT_INCLUDES := -Iplat/arm/board/fvp/include 103 104 105PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 106 107FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 108 109ifeq (${ARCH}, aarch64) 110 111# select a different set of CPU files, depending on whether we compile for 112# hardware assisted coherency cores or not 113ifeq (${HW_ASSISTED_COHERENCY}, 0) 114# Cores used without DSU 115 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 116 lib/cpus/aarch64/cortex_a53.S \ 117 lib/cpus/aarch64/cortex_a57.S \ 118 lib/cpus/aarch64/cortex_a72.S \ 119 lib/cpus/aarch64/cortex_a73.S 120else 121# Cores used with DSU only 122 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 123 # AArch64-only cores 124 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 125 lib/cpus/aarch64/cortex_a76ae.S \ 126 lib/cpus/aarch64/cortex_a77.S \ 127 lib/cpus/aarch64/cortex_a78.S \ 128 lib/cpus/aarch64/neoverse_n_common.S \ 129 lib/cpus/aarch64/neoverse_n1.S \ 130 lib/cpus/aarch64/neoverse_n2.S \ 131 lib/cpus/aarch64/neoverse_e1.S \ 132 lib/cpus/aarch64/neoverse_v1.S \ 133 lib/cpus/aarch64/cortex_a78_ae.S \ 134 lib/cpus/aarch64/cortex_a510.S \ 135 lib/cpus/aarch64/cortex_a710.S \ 136 lib/cpus/aarch64/cortex_makalu.S \ 137 lib/cpus/aarch64/cortex_makalu_elp_arm.S \ 138 lib/cpus/aarch64/cortex_a65.S \ 139 lib/cpus/aarch64/cortex_a65ae.S \ 140 lib/cpus/aarch64/cortex_a78c.S 141 endif 142 # AArch64/AArch32 cores 143 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 144 lib/cpus/aarch64/cortex_a75.S 145endif 146 147else 148FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 149endif 150 151BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 152 drivers/arm/sp805/sp805.c \ 153 drivers/delay_timer/delay_timer.c \ 154 drivers/io/io_semihosting.c \ 155 lib/semihosting/semihosting.c \ 156 lib/semihosting/${ARCH}/semihosting_call.S \ 157 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 158 plat/arm/board/fvp/fvp_bl1_setup.c \ 159 plat/arm/board/fvp/fvp_err.c \ 160 plat/arm/board/fvp/fvp_io_storage.c \ 161 ${FVP_CPU_LIBS} \ 162 ${FVP_INTERCONNECT_SOURCES} 163 164ifeq (${USE_SP804_TIMER},1) 165BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 166else 167BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 168endif 169 170 171BL2_SOURCES += drivers/arm/sp805/sp805.c \ 172 drivers/io/io_semihosting.c \ 173 lib/utils/mem_region.c \ 174 lib/semihosting/semihosting.c \ 175 lib/semihosting/${ARCH}/semihosting_call.S \ 176 plat/arm/board/fvp/fvp_bl2_setup.c \ 177 plat/arm/board/fvp/fvp_err.c \ 178 plat/arm/board/fvp/fvp_io_storage.c \ 179 plat/arm/common/arm_nor_psci_mem_protect.c \ 180 ${FVP_SECURITY_SOURCES} 181 182 183ifeq (${COT_DESC_IN_DTB},1) 184BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 185endif 186 187ifeq (${BL2_AT_EL3},1) 188BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 189 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 190 ${FVP_CPU_LIBS} \ 191 ${FVP_INTERCONNECT_SOURCES} 192endif 193 194ifeq (${USE_SP804_TIMER},1) 195BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 196endif 197 198BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 199 ${FVP_SECURITY_SOURCES} 200 201ifeq (${USE_SP804_TIMER},1) 202BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 203endif 204 205BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 206 drivers/arm/smmu/smmu_v3.c \ 207 drivers/delay_timer/delay_timer.c \ 208 drivers/cfi/v2m/v2m_flash.c \ 209 lib/utils/mem_region.c \ 210 plat/arm/board/fvp/fvp_bl31_setup.c \ 211 plat/arm/board/fvp/fvp_console.c \ 212 plat/arm/board/fvp/fvp_pm.c \ 213 plat/arm/board/fvp/fvp_topology.c \ 214 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 215 plat/arm/common/arm_nor_psci_mem_protect.c \ 216 ${FVP_CPU_LIBS} \ 217 ${FVP_GIC_SOURCES} \ 218 ${FVP_INTERCONNECT_SOURCES} \ 219 ${FVP_SECURITY_SOURCES} 220 221# Support for fconf in BL31 222# Added separately from the above list for better readability 223ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 224BL31_SOURCES += common/fdt_wrappers.c \ 225 lib/fconf/fconf.c \ 226 lib/fconf/fconf_dyn_cfg_getter.c \ 227 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 228 229ifeq (${SEC_INT_DESC_IN_FCONF},1) 230BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 231endif 232 233endif 234 235ifeq (${USE_SP804_TIMER},1) 236BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 237else 238BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 239endif 240 241# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 242ifdef UNIX_MK 243FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 244FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 245 ${PLAT}_fw_config.dts \ 246 ${PLAT}_tb_fw_config.dts \ 247 ${PLAT}_soc_fw_config.dts \ 248 ${PLAT}_nt_fw_config.dts \ 249 ) 250 251FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 252FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 253FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 254FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 255 256ifeq (${SPD},tspd) 257FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 258FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 259 260# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 261$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 262endif 263 264ifeq (${SPD},spmd) 265 266ifeq ($(ARM_SPMC_MANIFEST_DTS),) 267ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 268endif 269 270FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 271FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 272 273# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 274$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 275endif 276 277# Add the FW_CONFIG to FIP and specify the same to certtool 278$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 279# Add the TB_FW_CONFIG to FIP and specify the same to certtool 280$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 281# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 282$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 283# Add the NT_FW_CONFIG to FIP and specify the same to certtool 284$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 285 286FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 287$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 288 289# Add the HW_CONFIG to FIP and specify the same to certtool 290$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 291endif 292 293# Enable Activity Monitor Unit extensions by default 294ENABLE_AMU := 1 295 296# Enable dynamic mitigation support by default 297DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 298 299# Enable reclaiming of BL31 initialisation code for secondary cores 300# stacks for FVP. However, don't enable reclaiming for clang. 301ifneq (${RESET_TO_BL31},1) 302ifeq ($(findstring clang,$(notdir $(CC))),) 303RECLAIM_INIT_CODE := 1 304endif 305endif 306 307ifeq (${ENABLE_AMU},1) 308BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 309 lib/cpus/aarch64/cpuamu_helpers.S 310 311ifeq (${HW_ASSISTED_COHERENCY}, 1) 312BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 313 lib/cpus/aarch64/neoverse_n1_pubsub.c 314endif 315endif 316 317ifeq (${RAS_EXTENSION},1) 318BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 319endif 320 321ifneq (${ENABLE_STACK_PROTECTOR},0) 322PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 323endif 324 325ifeq (${ARCH},aarch32) 326 NEED_BL32 := yes 327endif 328 329# Enable the dynamic translation tables library. 330ifeq (${ARCH},aarch32) 331 ifeq (${RESET_TO_SP_MIN},1) 332 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 333 endif 334else # AArch64 335 ifeq (${RESET_TO_BL31},1) 336 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 337 endif 338 ifeq (${SPD},trusty) 339 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 340 endif 341endif 342 343ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 344 ifeq (${ARCH},aarch32) 345 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 346 else # AArch64 347 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 348 ifeq (${SPD},tspd) 349 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 350 endif 351 endif 352endif 353 354ifeq (${USE_DEBUGFS},1) 355 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 356endif 357 358# Add support for platform supplied linker script for BL31 build 359$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 360 361ifneq (${BL2_AT_EL3}, 0) 362 override BL1_SOURCES = 363endif 364 365include plat/arm/board/common/board_common.mk 366include plat/arm/common/arm_common.mk 367 368ifeq (${TRUSTED_BOARD_BOOT}, 1) 369BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 370BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 371 372ifeq (${MEASURED_BOOT},1) 373BL2_SOURCES += plat/arm/board/fvp/fvp_measured_boot.c 374endif 375 376# FVP being a development platform, enable capability to disable Authentication 377# dynamically if TRUSTED_BOARD_BOOT is set. 378DYN_DISABLE_AUTH := 1 379endif 380