1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. This option defaults to 256. 34FVP_TRUSTED_SRAM_SIZE := 256 35 36# Macro to enable helpers for running SPM tests. Disabled by default. 37PLAT_TEST_SPM := 0 38 39# By default dont build CPUs with no FVP model. 40BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 41 42ENABLE_FEAT_AMU := 2 43ENABLE_FEAT_AMUv1p1 := 2 44ENABLE_FEAT_HCX := 2 45ENABLE_FEAT_RNG := 2 46ENABLE_FEAT_TWED := 2 47ENABLE_FEAT_GCS := 2 48 49ifeq (${ARCH}, aarch64) 50 51ifeq (${SPM_MM}, 0) 52ifeq (${CTX_INCLUDE_FPREGS}, 0) 53 ENABLE_SME_FOR_NS := 2 54 ENABLE_SME2_FOR_NS := 2 55else 56 ENABLE_SVE_FOR_NS := 0 57 ENABLE_SME_FOR_NS := 0 58 ENABLE_SME2_FOR_NS := 0 59endif 60endif 61 62 ENABLE_BRBE_FOR_NS := 2 63 ENABLE_TRBE_FOR_NS := 2 64 ENABLE_FEAT_D128 := 2 65 ENABLE_FEAT_FPMR := 2 66 ENABLE_FEAT_MOPS := 2 67endif 68 69ENABLE_SYS_REG_TRACE_FOR_NS := 2 70ENABLE_FEAT_CSV2_2 := 2 71ENABLE_FEAT_CSV2_3 := 2 72ENABLE_FEAT_DEBUGV8P9 := 2 73ENABLE_FEAT_DIT := 2 74ENABLE_FEAT_PAN := 2 75ENABLE_FEAT_VHE := 2 76CTX_INCLUDE_NEVE_REGS := 2 77ENABLE_FEAT_SEL2 := 2 78ENABLE_TRF_FOR_NS := 2 79ENABLE_FEAT_ECV := 2 80ENABLE_FEAT_FGT := 2 81ENABLE_FEAT_FGT2 := 2 82ENABLE_FEAT_THE := 2 83ENABLE_FEAT_TCR2 := 2 84ENABLE_FEAT_S2PIE := 2 85ENABLE_FEAT_S1PIE := 2 86ENABLE_FEAT_S2POE := 2 87ENABLE_FEAT_S1POE := 2 88ENABLE_FEAT_SCTLR2 := 2 89ENABLE_FEAT_MTE2 := 2 90ENABLE_FEAT_LS64_ACCDATA := 2 91 92# The FVP platform depends on this macro to build with correct GIC driver. 93$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 94 95# Pass FVP_CLUSTER_COUNT to the build system. 96$(eval $(call add_define,FVP_CLUSTER_COUNT)) 97 98# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 99$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 100 101# Pass FVP_MAX_PE_PER_CPU to the build system. 102$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 103 104# Pass FVP_GICR_REGION_PROTECTION to the build system. 105$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 106 107# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 108$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 109 110# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 111# choose the CCI driver , else the CCN driver 112ifeq ($(FVP_CLUSTER_COUNT), 0) 113$(error "Incorrect cluster count specified for FVP port") 114else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 115FVP_INTERCONNECT_DRIVER := FVP_CCI 116else 117FVP_INTERCONNECT_DRIVER := FVP_CCN 118endif 119 120$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 121 122# Choose the GIC sources depending upon the how the FVP will be invoked 123ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 124 125# The GIC model (GIC-600 or GIC-500) will be detected at runtime 126GICV3_SUPPORT_GIC600 := 1 127GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 128 129# Include GICv3 driver files 130include drivers/arm/gic/v3/gicv3.mk 131 132FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 133 plat/common/plat_gicv3.c \ 134 plat/arm/common/arm_gicv3.c 135 136 ifeq ($(filter 1,${RESET_TO_BL2} \ 137 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 138 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139 endif 140 141else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 142 143# No GICv4 extension 144GIC_ENABLE_V4_EXTN := 0 145$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 146 147# Include GICv2 driver files 148include drivers/arm/gic/v2/gicv2.mk 149 150FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 151 plat/common/plat_gicv2.c \ 152 plat/arm/common/arm_gicv2.c 153 154FVP_DT_PREFIX := fvp-base-gicv2-psci 155else 156$(error "Incorrect GIC driver chosen on FVP port") 157endif 158 159ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 160FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 161else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 162FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 163 plat/arm/common/arm_ccn.c 164else 165$(error "Incorrect CCN driver chosen on FVP port") 166endif 167 168FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 169 plat/arm/board/fvp/fvp_security.c \ 170 plat/arm/common/arm_tzc400.c 171 172 173PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 174 -Iinclude/lib/psa 175 176 177PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 178 179FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 180 181ifeq (${ARCH}, aarch64) 182 183# select a different set of CPU files, depending on whether we compile for 184# hardware assisted coherency cores or not 185ifeq (${HW_ASSISTED_COHERENCY}, 0) 186# Cores used without DSU 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 188 lib/cpus/aarch64/cortex_a53.S \ 189 lib/cpus/aarch64/cortex_a57.S \ 190 lib/cpus/aarch64/cortex_a72.S \ 191 lib/cpus/aarch64/cortex_a73.S 192else 193# Cores used with DSU only 194 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 195 # AArch64-only cores 196 # TODO: add all cores to the appropriate lists 197 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 198 lib/cpus/aarch64/cortex_a65ae.S \ 199 lib/cpus/aarch64/cortex_a76.S \ 200 lib/cpus/aarch64/cortex_a76ae.S \ 201 lib/cpus/aarch64/cortex_a77.S \ 202 lib/cpus/aarch64/cortex_a78.S \ 203 lib/cpus/aarch64/cortex_a78_ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_a710.S \ 206 lib/cpus/aarch64/cortex_a715.S \ 207 lib/cpus/aarch64/cortex_a720.S \ 208 lib/cpus/aarch64/cortex_a720_ae.S \ 209 lib/cpus/aarch64/neoverse_n_common.S \ 210 lib/cpus/aarch64/neoverse_n1.S \ 211 lib/cpus/aarch64/neoverse_n2.S \ 212 lib/cpus/aarch64/neoverse_v1.S \ 213 lib/cpus/aarch64/neoverse_e1.S \ 214 lib/cpus/aarch64/cortex_x2.S \ 215 lib/cpus/aarch64/cortex_x4.S 216 endif 217 # AArch64/AArch32 cores 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 219 lib/cpus/aarch64/cortex_a75.S 220endif 221 222#Build AArch64-only CPUs with no FVP model yet. 223ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 224 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 225 lib/cpus/aarch64/cortex_gelas.S \ 226 lib/cpus/aarch64/nevis.S \ 227 lib/cpus/aarch64/travis.S \ 228 lib/cpus/aarch64/cortex_arcadia.S \ 229 lib/cpus/aarch64/cortex_alto.S 230endif 231 232else 233FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 234 lib/cpus/aarch32/cortex_a57.S \ 235 lib/cpus/aarch32/cortex_a53.S 236endif 237 238BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 239 drivers/arm/sp805/sp805.c \ 240 drivers/delay_timer/delay_timer.c \ 241 drivers/io/io_semihosting.c \ 242 lib/semihosting/semihosting.c \ 243 lib/semihosting/${ARCH}/semihosting_call.S \ 244 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 245 plat/arm/board/fvp/fvp_bl1_setup.c \ 246 plat/arm/board/fvp/fvp_cpu_pwr.c \ 247 plat/arm/board/fvp/fvp_err.c \ 248 plat/arm/board/fvp/fvp_io_storage.c \ 249 plat/arm/board/fvp/fvp_topology.c \ 250 ${FVP_CPU_LIBS} \ 251 ${FVP_INTERCONNECT_SOURCES} 252 253ifeq (${USE_SP804_TIMER},1) 254BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 255else 256BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 257endif 258 259 260BL2_SOURCES += drivers/arm/sp805/sp805.c \ 261 drivers/io/io_semihosting.c \ 262 lib/utils/mem_region.c \ 263 lib/semihosting/semihosting.c \ 264 lib/semihosting/${ARCH}/semihosting_call.S \ 265 plat/arm/board/fvp/fvp_bl2_setup.c \ 266 plat/arm/board/fvp/fvp_err.c \ 267 plat/arm/board/fvp/fvp_io_storage.c \ 268 plat/arm/common/arm_nor_psci_mem_protect.c \ 269 ${FVP_SECURITY_SOURCES} 270 271 272ifeq (${COT_DESC_IN_DTB},1) 273BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 274endif 275 276ifeq (${ENABLE_RME},1) 277BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 278 plat/arm/board/fvp/fvp_cpu_pwr.c 279 280BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 281 plat/arm/board/fvp/fvp_realm_attest_key.c \ 282 plat/arm/board/fvp/fvp_el3_token_sign.c 283endif 284 285ifeq (${ENABLE_FEAT_RNG_TRAP},1) 286BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 287endif 288 289ifeq (${RESET_TO_BL2},1) 290BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 291 plat/arm/board/fvp/fvp_cpu_pwr.c \ 292 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 293 ${FVP_CPU_LIBS} \ 294 ${FVP_INTERCONNECT_SOURCES} 295endif 296 297ifeq (${USE_SP804_TIMER},1) 298BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 299endif 300 301BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 302 ${FVP_SECURITY_SOURCES} 303 304ifeq (${USE_SP804_TIMER},1) 305BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 306endif 307 308BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 309 drivers/arm/smmu/smmu_v3.c \ 310 drivers/delay_timer/delay_timer.c \ 311 drivers/cfi/v2m/v2m_flash.c \ 312 lib/utils/mem_region.c \ 313 plat/arm/board/fvp/fvp_bl31_setup.c \ 314 plat/arm/board/fvp/fvp_console.c \ 315 plat/arm/board/fvp/fvp_pm.c \ 316 plat/arm/board/fvp/fvp_topology.c \ 317 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 318 plat/arm/board/fvp/fvp_cpu_pwr.c \ 319 plat/arm/common/arm_nor_psci_mem_protect.c \ 320 ${FVP_CPU_LIBS} \ 321 ${FVP_GIC_SOURCES} \ 322 ${FVP_INTERCONNECT_SOURCES} \ 323 ${FVP_SECURITY_SOURCES} 324 325# Support for fconf in BL31 326# Added separately from the above list for better readability 327ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 328BL31_SOURCES += lib/fconf/fconf.c \ 329 lib/fconf/fconf_dyn_cfg_getter.c \ 330 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 331 332BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 333 334ifeq (${SEC_INT_DESC_IN_FCONF},1) 335BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 336endif 337 338endif 339 340ifeq (${USE_SP804_TIMER},1) 341BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 342else 343BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 344endif 345 346# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 347FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 348 349FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 350$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 351 352ifeq (${TRANSFER_LIST}, 0) 353FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 354 ${PLAT}_fw_config.dts \ 355 ${PLAT}_tb_fw_config.dts \ 356 ${PLAT}_soc_fw_config.dts \ 357 ${PLAT}_nt_fw_config.dts \ 358 ) 359 360FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 361FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 362FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 363FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 364 365ifeq (${SPD},tspd) 366FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 367FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 368 369# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 371endif 372 373ifeq (${SPD},spmd) 374 375ifeq ($(ARM_SPMC_MANIFEST_DTS),) 376ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 377endif 378 379FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 380FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 381 382# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 384endif 385 386# Add the FW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 388# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 389$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 390# Add the NT_FW_CONFIG to FIP and specify the same to certtool 391$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 392# Add the TB_FW_CONFIG to FIP and specify the same to certtool 393$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 394endif 395 396# Add the HW_CONFIG to FIP and specify the same to certtool 397$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 398 399ifeq (${TRANSFER_LIST}, 1) 400include lib/transfer_list/transfer_list.mk 401 402ifeq ($(RESET_TO_BL31), 1) 403HW_CONFIG := ${FVP_HW_CONFIG} 404FW_HANDOFF_SIZE := 20000 405 406TRANSFER_LIST_DTB_OFFSET := 0x20 407$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 408endif 409endif 410 411ifeq (${HOB_LIST}, 1) 412include lib/hob/hob.mk 413endif 414 415# Enable dynamic mitigation support by default 416DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 417 418ifneq (${ENABLE_FEAT_AMU},0) 419BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 420 lib/cpus/aarch64/cpuamu_helpers.S 421 422ifeq (${HW_ASSISTED_COHERENCY}, 1) 423BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 424 lib/cpus/aarch64/neoverse_n1_pubsub.c 425endif 426endif 427 428ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 429 ifeq (${ENABLE_FEAT_RAS},1) 430 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 431 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 432 else 433 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 434 endif 435 else 436 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 437 endif 438endif 439 440ifneq (${ENABLE_STACK_PROTECTOR},0) 441PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 442endif 443 444# Enable the dynamic translation tables library. 445ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 446 ifeq (${ARCH},aarch32) 447 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 448 else # AArch64 449 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 450 endif 451endif 452 453ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 454 ifeq (${ARCH},aarch32) 455 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 456 else # AArch64 457 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 458 ifeq (${SPD},tspd) 459 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 460 endif 461 endif 462endif 463 464ifeq (${USE_DEBUGFS},1) 465 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 466endif 467 468# Add support for platform supplied linker script for BL31 build 469$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 470 471ifneq (${RESET_TO_BL2}, 0) 472 override BL1_SOURCES = 473endif 474 475include plat/arm/board/common/board_common.mk 476include plat/arm/common/arm_common.mk 477 478ifeq (${MEASURED_BOOT},1) 479BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 480 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 481 lib/psa/measured_boot.c 482 483BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 484 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 485 lib/psa/measured_boot.c 486endif 487 488ifeq (${DRTM_SUPPORT}, 1) 489BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 490 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 491 plat/arm/board/fvp/fvp_drtm_err.c \ 492 plat/arm/board/fvp/fvp_drtm_measurement.c \ 493 plat/arm/board/fvp/fvp_drtm_stub.c \ 494 plat/arm/common/arm_dyn_cfg.c \ 495 plat/arm/board/fvp/fvp_err.c 496endif 497 498ifeq (${TRUSTED_BOARD_BOOT}, 1) 499BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 500BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 501 502# FVP being a development platform, enable capability to disable Authentication 503# dynamically if TRUSTED_BOARD_BOOT is set. 504DYN_DISABLE_AUTH := 1 505endif 506 507ifeq (${SPMC_AT_EL3}, 1) 508PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 509endif 510 511PSCI_OS_INIT_MODE := 1 512 513ifeq (${SPD},spmd) 514BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 515endif 516 517# Test specific macros, keep them at bottom of this file 518$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 519ifeq (${PLATFORM_TEST_EA_FFH}, 1) 520 ifeq (${FFH_SUPPORT}, 0) 521 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 522 endif 523 524endif 525 526$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 527ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 528 ifeq (${ENABLE_FEAT_RAS}, 0) 529 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 530 endif 531 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 532 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 533 endif 534endif 535 536$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 537ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 538 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 539 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 540 endif 541 ifeq (${ENABLE_SPMD_LP}, 0) 542 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 543 endif 544 ifeq (${ENABLE_FEAT_RAS}, 0) 545 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 546 endif 547 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 548 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 549 endif 550endif 551 552ifeq (${ERRATA_ABI_SUPPORT}, 1) 553include plat/arm/board/fvp/fvp_cpu_errata.mk 554endif 555 556# Build macro necessary for running SPM tests on FVP platform 557$(eval $(call add_define,PLAT_TEST_SPM)) 558