1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 70 ENABLE_FEAT_CPA2 := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_CLRBHB := 2 77ENABLE_FEAT_DEBUGV8P9 := 2 78ENABLE_FEAT_DIT := 2 79ENABLE_FEAT_PAN := 2 80ENABLE_FEAT_VHE := 2 81CTX_INCLUDE_NEVE_REGS := 2 82ENABLE_FEAT_SEL2 := 2 83ENABLE_TRF_FOR_NS := 2 84ENABLE_FEAT_ECV := 2 85ENABLE_FEAT_FGT := 2 86ENABLE_FEAT_FGT2 := 2 87ENABLE_FEAT_THE := 2 88ENABLE_FEAT_TCR2 := 2 89ENABLE_FEAT_S2PIE := 2 90ENABLE_FEAT_S1PIE := 2 91ENABLE_FEAT_S2POE := 2 92ENABLE_FEAT_S1POE := 2 93ENABLE_FEAT_SCTLR2 := 2 94ENABLE_FEAT_MTE2 := 2 95ENABLE_FEAT_LS64_ACCDATA := 2 96ENABLE_FEAT_AIE := 2 97ENABLE_FEAT_PFAR := 2 98ENABLE_FEAT_EBEP := 2 99 100ifeq (${ENABLE_RME},1) 101 ENABLE_FEAT_MEC := 2 102 RMMD_ENABLE_IDE_KEY_PROG := 1 103endif 104 105# The FVP platform depends on this macro to build with correct GIC driver. 106$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 107 108# Pass FVP_CLUSTER_COUNT to the build system. 109$(eval $(call add_define,FVP_CLUSTER_COUNT)) 110 111# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 112$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 113 114# Pass FVP_MAX_PE_PER_CPU to the build system. 115$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 116 117# Pass FVP_GICR_REGION_PROTECTION to the build system. 118$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 119 120# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 121$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 122 123# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 124# choose the CCI driver , else the CCN driver 125ifeq ($(FVP_CLUSTER_COUNT), 0) 126$(error "Incorrect cluster count specified for FVP port") 127else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 128FVP_INTERCONNECT_DRIVER := FVP_CCI 129else 130FVP_INTERCONNECT_DRIVER := FVP_CCN 131endif 132 133$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 134 135# Choose the GIC sources depending upon the how the FVP will be invoked 136ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 137USE_GIC_DRIVER := 3 138 139# The GIC model (GIC-600 or GIC-500) will be detected at runtime 140GICV3_SUPPORT_GIC600 := 1 141GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 142 143FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 144ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 145BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 146endif 147 148ifeq (${HW_ASSISTED_COHERENCY}, 0) 149FVP_DT_PREFIX := fvp-base-gicv3-psci 150else 151FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 152endif 153else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 154USE_GIC_DRIVER := 5 155ENABLE_FEAT_GCIE := 1 156BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 157FVP_DT_PREFIX := fvp-base-gicv5-psci 158ifneq ($(SPD),none) 159 $(error Error: GICv5 is not compatible with SPDs) 160endif 161ifeq ($(ENABLE_RME),1) 162 $(error Error: GICv5 is not compatible with RME) 163endif 164else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 165USE_GIC_DRIVER := 2 166 167# No GICv4 extension 168GIC_ENABLE_V4_EXTN := 0 169$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 170 171FVP_DT_PREFIX := fvp-base-gicv2-psci 172else 173$(error "Incorrect GIC driver chosen on FVP port") 174endif 175 176ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 177FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 178else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 179FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 180 plat/arm/common/arm_ccn.c 181else 182$(error "Incorrect CCN driver chosen on FVP port") 183endif 184 185FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 186 plat/arm/board/fvp/fvp_security.c \ 187 plat/arm/common/arm_tzc400.c 188 189 190PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 191 -Iinclude/lib/psa 192 193 194PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 195 196FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 197 198ifeq (${ARCH}, aarch64) 199 200# select a different set of CPU files, depending on whether we compile for 201# hardware assisted coherency cores or not 202ifeq (${HW_ASSISTED_COHERENCY}, 0) 203# Cores used without DSU 204 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 205 lib/cpus/aarch64/cortex_a53.S \ 206 lib/cpus/aarch64/cortex_a57.S \ 207 lib/cpus/aarch64/cortex_a72.S \ 208 lib/cpus/aarch64/cortex_a73.S 209else 210# Cores used with DSU only 211 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 212 # AArch64-only cores 213 # TODO: add all cores to the appropriate lists 214 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 215 lib/cpus/aarch64/cortex_a65ae.S \ 216 lib/cpus/aarch64/cortex_a76.S \ 217 lib/cpus/aarch64/cortex_a76ae.S \ 218 lib/cpus/aarch64/cortex_a77.S \ 219 lib/cpus/aarch64/cortex_a78.S \ 220 lib/cpus/aarch64/cortex_a78_ae.S \ 221 lib/cpus/aarch64/cortex_a78c.S \ 222 lib/cpus/aarch64/cortex_a710.S \ 223 lib/cpus/aarch64/cortex_a715.S \ 224 lib/cpus/aarch64/cortex_a720.S \ 225 lib/cpus/aarch64/cortex_a720_ae.S \ 226 lib/cpus/aarch64/neoverse_n1.S \ 227 lib/cpus/aarch64/neoverse_n2.S \ 228 lib/cpus/aarch64/neoverse_v1.S \ 229 lib/cpus/aarch64/neoverse_e1.S \ 230 lib/cpus/aarch64/cortex_x2.S \ 231 lib/cpus/aarch64/cortex_x4.S 232 endif 233 # AArch64/AArch32 cores 234 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 235 lib/cpus/aarch64/cortex_a75.S 236endif 237 238#Include all CPUs to build to support all-errata build. 239ifeq (${ENABLE_ERRATA_ALL},1) 240 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 241 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 242 lib/cpus/aarch64/cortex_a510.S \ 243 lib/cpus/aarch64/cortex_a520.S \ 244 lib/cpus/aarch64/cortex_a725.S \ 245 lib/cpus/aarch64/cortex_x1.S \ 246 lib/cpus/aarch64/cortex_x3.S \ 247 lib/cpus/aarch64/cortex_x925.S \ 248 lib/cpus/aarch64/neoverse_n3.S \ 249 lib/cpus/aarch64/neoverse_v2.S \ 250 lib/cpus/aarch64/neoverse_v3.S 251endif 252 253#Build AArch64-only CPUs with no FVP model yet. 254ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 255 ERRATA_SME_POWER_DOWN := 1 256 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 257 lib/cpus/aarch64/c1_nano.S \ 258 lib/cpus/aarch64/c1_ultra.S \ 259 lib/cpus/aarch64/c1_premium.S \ 260 lib/cpus/aarch64/canyon.S \ 261 lib/cpus/aarch64/caddo.S \ 262 lib/cpus/aarch64/veymont.S \ 263 lib/cpus/aarch64/dionysus.S \ 264 lib/cpus/aarch64/venom.S 265endif 266 267else 268FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 269 lib/cpus/aarch32/cortex_a57.S \ 270 lib/cpus/aarch32/cortex_a53.S 271endif 272 273BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 274 drivers/arm/sp805/sp805.c \ 275 drivers/delay_timer/delay_timer.c \ 276 drivers/io/io_semihosting.c \ 277 lib/semihosting/semihosting.c \ 278 lib/semihosting/${ARCH}/semihosting_call.S \ 279 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 280 plat/arm/board/fvp/fvp_bl1_setup.c \ 281 plat/arm/board/fvp/fvp_cpu_pwr.c \ 282 plat/arm/board/fvp/fvp_err.c \ 283 plat/arm/board/fvp/fvp_io_storage.c \ 284 plat/arm/board/fvp/fvp_topology.c \ 285 ${FVP_CPU_LIBS} \ 286 ${FVP_INTERCONNECT_SOURCES} 287 288ifeq (${USE_SP804_TIMER},1) 289BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 290else 291BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 292endif 293 294 295BL2_SOURCES += drivers/arm/sp805/sp805.c \ 296 drivers/io/io_semihosting.c \ 297 lib/utils/mem_region.c \ 298 lib/semihosting/semihosting.c \ 299 lib/semihosting/${ARCH}/semihosting_call.S \ 300 plat/arm/board/fvp/fvp_bl2_setup.c \ 301 plat/arm/board/fvp/fvp_err.c \ 302 plat/arm/board/fvp/fvp_io_storage.c \ 303 plat/arm/common/arm_nor_psci_mem_protect.c \ 304 ${FVP_SECURITY_SOURCES} 305 306 307ifeq (${COT_DESC_IN_DTB},1) 308BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 309endif 310 311ifeq (${ENABLE_RME},1) 312BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 313 plat/arm/board/fvp/fvp_cpu_pwr.c 314 315BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 316 plat/arm/board/fvp/fvp_realm_attest_key.c \ 317 plat/arm/board/fvp/fvp_el3_token_sign.c \ 318 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 319 plat/arm/common/plat_rmm_mem_carveout.c 320endif 321 322ifneq (${ENABLE_FEAT_RNG_TRAP},0) 323BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 324endif 325 326ifeq (${RESET_TO_BL2},1) 327BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 328 plat/arm/board/fvp/fvp_cpu_pwr.c \ 329 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 330 ${FVP_CPU_LIBS} \ 331 ${FVP_INTERCONNECT_SOURCES} 332endif 333 334ifeq (${USE_SP804_TIMER},1) 335BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 336endif 337 338BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 339 ${FVP_SECURITY_SOURCES} 340 341ifeq (${USE_SP804_TIMER},1) 342BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 343endif 344 345BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 346 drivers/arm/smmu/smmu_v3.c \ 347 drivers/delay_timer/delay_timer.c \ 348 drivers/cfi/v2m/v2m_flash.c \ 349 lib/utils/mem_region.c \ 350 plat/arm/board/fvp/fvp_bl31_setup.c \ 351 plat/arm/board/fvp/fvp_console.c \ 352 plat/arm/board/fvp/fvp_pm.c \ 353 plat/arm/board/fvp/fvp_topology.c \ 354 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 355 plat/arm/board/fvp/fvp_cpu_pwr.c \ 356 plat/arm/common/arm_nor_psci_mem_protect.c \ 357 ${FVP_CPU_LIBS} \ 358 ${FVP_INTERCONNECT_SOURCES} \ 359 ${FVP_SECURITY_SOURCES} 360 361# Support for fconf in BL31 362# Added separately from the above list for better readability 363ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 364BL31_SOURCES += lib/fconf/fconf.c \ 365 lib/fconf/fconf_dyn_cfg_getter.c \ 366 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 367 368BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 369 370ifeq (${SEC_INT_DESC_IN_FCONF},1) 371BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 372endif 373 374endif 375 376ifeq (${USE_SP804_TIMER},1) 377BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 378else 379BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 380endif 381 382# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 383FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 384 385FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 386$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 387HW_CONFIG := ${FVP_HW_CONFIG} 388 389HW_CONFIG_BASE ?= 0x82000000 390 391# Set default initrd base 128MiB offset of the default kernel address in FVP 392INITRD_BASE ?= 0x90000000 393 394# Kernel base address supports Linux kernels before v5.7 395# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 396ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 397 PRELOADED_BL33_BASE ?= 0x80080000 398 ifeq (${RESET_TO_BL31},1) 399 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 400 endif 401endif 402 403ifeq (${TRANSFER_LIST}, 0) 404FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 405 ${PLAT}_fw_config.dts \ 406 ${PLAT}_tb_fw_config.dts \ 407 ${PLAT}_soc_fw_config.dts \ 408 ${PLAT}_nt_fw_config.dts \ 409 ) 410 411FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 412FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 413FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 414FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 415 416ifeq (${SPD},tspd) 417FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 418FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 419 420# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 421$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 422endif 423 424# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 425$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 426# Add the NT_FW_CONFIG to FIP and specify the same to certtool 427$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 428endif 429 430ifeq (${SPD},spmd) 431 432ifeq ($(ARM_SPMC_MANIFEST_DTS),) 433ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 434endif 435 436FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 437FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 438 439# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 440$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 441endif 442 443# Add the HW_CONFIG to FIP and specify the same to certtool 444$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 445 446ifeq (${TRANSFER_LIST}, 1) 447 448ifeq ($(RESET_TO_BL31), 1) 449FW_HANDOFF_SIZE := 20000 450 451TRANSFER_LIST_DTB_OFFSET := 0x20 452$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 453endif 454endif 455 456ifeq (${HOB_LIST}, 1) 457include lib/hob/hob.mk 458endif 459 460# Enable dynamic mitigation support by default 461DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 462 463ifneq (${ENABLE_FEAT_AMU},0) 464BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 465 lib/cpus/aarch64/cpuamu_helpers.S 466 467ifeq (${HW_ASSISTED_COHERENCY}, 1) 468BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 469 lib/cpus/aarch64/neoverse_n1_pubsub.c 470endif 471endif 472 473ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 474 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 475 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 476 endif 477 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 478 plat/arm/board/fvp/aarch64/fvp_ea.c 479endif 480 481ifneq (${ENABLE_STACK_PROTECTOR},0) 482PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 483endif 484 485# Enable the dynamic translation tables library. 486ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 487 ifeq (${ARCH},aarch32) 488 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 489 else # AArch64 490 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 491 endif 492endif 493 494ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 495 ifeq (${ARCH},aarch32) 496 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 497 else # AArch64 498 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 499 ifeq (${SPD},tspd) 500 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 501 endif 502 endif 503endif 504 505ifeq (${USE_DEBUGFS},1) 506 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 507endif 508 509# Add support for platform supplied linker script for BL31 build 510PLAT_EXTRA_LD_SCRIPT := 1 511 512ifneq (${RESET_TO_BL2}, 0) 513 override BL1_SOURCES = 514endif 515 516include plat/arm/board/common/board_common.mk 517include plat/arm/common/arm_common.mk 518 519ifeq (${MEASURED_BOOT},1) 520BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 521 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 522 lib/psa/measured_boot.c 523 524BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 525 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 526 lib/psa/measured_boot.c 527endif 528 529ifeq (${DRTM_SUPPORT}, 1) 530BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 531 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 532 plat/arm/board/fvp/fvp_drtm_err.c \ 533 plat/arm/board/fvp/fvp_drtm_measurement.c \ 534 plat/arm/board/fvp/fvp_drtm_stub.c \ 535 plat/arm/common/arm_dyn_cfg.c \ 536 plat/arm/board/fvp/fvp_err.c 537endif 538 539ifeq (${TRUSTED_BOARD_BOOT}, 1) 540BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 541BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 542 543# FVP being a development platform, enable capability to disable Authentication 544# dynamically if TRUSTED_BOARD_BOOT is set. 545DYN_DISABLE_AUTH := 1 546endif 547 548ifeq (${SPMC_AT_EL3}, 1) 549PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 550endif 551 552PSCI_OS_INIT_MODE := 1 553 554ifeq (${SPD},spmd) 555BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 556endif 557 558# Test specific macros, keep them at bottom of this file 559$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 560ifeq (${PLATFORM_TEST_EA_FFH}, 1) 561 ifeq (${FFH_SUPPORT}, 0) 562 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 563 endif 564 565endif 566 567PLATFORM_TEST_RAS_FFH ?= 0 568$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 569ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 570 ifeq (${ENABLE_FEAT_RAS}, 0) 571 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 572 endif 573 ifeq (${SDEI_SUPPORT}, 0) 574 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 575 endif 576 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 577 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 578 endif 579endif 580 581$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 582ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 583 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 584 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 585 endif 586 ifeq (${ENABLE_SPMD_LP}, 0) 587 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 588 endif 589 ifeq (${ENABLE_FEAT_RAS}, 0) 590 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 591 endif 592 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 593 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 594 endif 595endif 596 597ifeq (${ERRATA_ABI_SUPPORT}, 1) 598include plat/arm/board/fvp/fvp_cpu_errata.mk 599endif 600 601# Build macro necessary for running SPM tests on FVP platform 602$(eval $(call add_define,PLAT_TEST_SPM)) 603 604ifeq (${LFA_SUPPORT},1) 605BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 606endif 607 608# This is set to 1 by default when the firmware update 609# support is enabled. Since the BL2 image is not updatable 610ifeq ($(PSA_FWU_SUPPORT),1) 611 SEPARATE_BL2_FIP := 1 612endif 613 614ifeq (${TRANSFER_LIST}, 0) 615ifeq (${SEPARATE_BL2_FIP},1) 616$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 617$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 618else 619$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 620$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 621endif 622endif 623