1# 2# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Pass FVP_GICR_REGION_PROTECTION to the build system. 40$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 41 42# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 43# choose the CCI driver , else the CCN driver 44ifeq ($(FVP_CLUSTER_COUNT), 0) 45$(error "Incorrect cluster count specified for FVP port") 46else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 47FVP_INTERCONNECT_DRIVER := FVP_CCI 48else 49FVP_INTERCONNECT_DRIVER := FVP_CCN 50endif 51 52$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 53 54# Choose the GIC sources depending upon the how the FVP will be invoked 55ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 56 57# The GIC model (GIC-600 or GIC-500) will be detected at runtime 58GICV3_SUPPORT_GIC600 := 1 59GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 60 61# Include GICv3 driver files 62include drivers/arm/gic/v3/gicv3.mk 63 64FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 65 plat/common/plat_gicv3.c \ 66 plat/arm/common/arm_gicv3.c 67 68 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 69 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 70 endif 71 72else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 73 74# No GICv4 extension 75GIC_ENABLE_V4_EXTN := 0 76$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 77 78# Include GICv2 driver files 79include drivers/arm/gic/v2/gicv2.mk 80 81FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 82 plat/common/plat_gicv2.c \ 83 plat/arm/common/arm_gicv2.c 84 85FVP_DT_PREFIX := fvp-base-gicv2-psci 86else 87$(error "Incorrect GIC driver chosen on FVP port") 88endif 89 90ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 91FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 92else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 93FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 94 plat/arm/common/arm_ccn.c 95else 96$(error "Incorrect CCN driver chosen on FVP port") 97endif 98 99FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 100 plat/arm/board/fvp/fvp_security.c \ 101 plat/arm/common/arm_tzc400.c 102 103 104PLAT_INCLUDES := -Iplat/arm/board/fvp/include 105 106 107PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 108 109FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 110 111ifeq (${ARCH}, aarch64) 112 113# select a different set of CPU files, depending on whether we compile for 114# hardware assisted coherency cores or not 115ifeq (${HW_ASSISTED_COHERENCY}, 0) 116# Cores used without DSU 117 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 118 lib/cpus/aarch64/cortex_a53.S \ 119 lib/cpus/aarch64/cortex_a57.S \ 120 lib/cpus/aarch64/cortex_a72.S \ 121 lib/cpus/aarch64/cortex_a73.S 122else 123# Cores used with DSU only 124 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 125 # AArch64-only cores 126 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 127 lib/cpus/aarch64/cortex_a76ae.S \ 128 lib/cpus/aarch64/cortex_a77.S \ 129 lib/cpus/aarch64/cortex_a78.S \ 130 lib/cpus/aarch64/neoverse_n_common.S \ 131 lib/cpus/aarch64/neoverse_n1.S \ 132 lib/cpus/aarch64/neoverse_n2.S \ 133 lib/cpus/aarch64/neoverse_e1.S \ 134 lib/cpus/aarch64/neoverse_v1.S \ 135 lib/cpus/aarch64/neoverse_demeter.S \ 136 lib/cpus/aarch64/cortex_a78_ae.S \ 137 lib/cpus/aarch64/cortex_a510.S \ 138 lib/cpus/aarch64/cortex_a710.S \ 139 lib/cpus/aarch64/cortex_a715.S \ 140 lib/cpus/aarch64/cortex_x3.S \ 141 lib/cpus/aarch64/cortex_a65.S \ 142 lib/cpus/aarch64/cortex_a65ae.S \ 143 lib/cpus/aarch64/cortex_a78c.S \ 144 lib/cpus/aarch64/cortex_hayes.S \ 145 lib/cpus/aarch64/cortex_hunter.S \ 146 lib/cpus/aarch64/cortex_x2.S \ 147 lib/cpus/aarch64/neoverse_poseidon.S 148 endif 149 # AArch64/AArch32 cores 150 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 151 lib/cpus/aarch64/cortex_a75.S 152endif 153 154else 155FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 156endif 157 158BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 159 drivers/arm/sp805/sp805.c \ 160 drivers/delay_timer/delay_timer.c \ 161 drivers/io/io_semihosting.c \ 162 lib/semihosting/semihosting.c \ 163 lib/semihosting/${ARCH}/semihosting_call.S \ 164 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 165 plat/arm/board/fvp/fvp_bl1_setup.c \ 166 plat/arm/board/fvp/fvp_err.c \ 167 plat/arm/board/fvp/fvp_io_storage.c \ 168 ${FVP_CPU_LIBS} \ 169 ${FVP_INTERCONNECT_SOURCES} 170 171ifeq (${USE_SP804_TIMER},1) 172BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 173else 174BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 175endif 176 177 178BL2_SOURCES += drivers/arm/sp805/sp805.c \ 179 drivers/io/io_semihosting.c \ 180 lib/utils/mem_region.c \ 181 lib/semihosting/semihosting.c \ 182 lib/semihosting/${ARCH}/semihosting_call.S \ 183 plat/arm/board/fvp/fvp_bl2_setup.c \ 184 plat/arm/board/fvp/fvp_err.c \ 185 plat/arm/board/fvp/fvp_io_storage.c \ 186 plat/arm/common/arm_nor_psci_mem_protect.c \ 187 ${FVP_SECURITY_SOURCES} 188 189 190ifeq (${COT_DESC_IN_DTB},1) 191BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 192endif 193 194ifeq (${ENABLE_RME},1) 195BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 196BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 197 plat/arm/board/fvp/fvp_realm_attest_key.c 198endif 199 200ifeq (${BL2_AT_EL3},1) 201BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 202 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 203 ${FVP_CPU_LIBS} \ 204 ${FVP_INTERCONNECT_SOURCES} 205endif 206 207ifeq (${USE_SP804_TIMER},1) 208BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 209endif 210 211BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 212 ${FVP_SECURITY_SOURCES} 213 214ifeq (${USE_SP804_TIMER},1) 215BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 216endif 217 218BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 219 drivers/arm/smmu/smmu_v3.c \ 220 drivers/delay_timer/delay_timer.c \ 221 drivers/cfi/v2m/v2m_flash.c \ 222 lib/utils/mem_region.c \ 223 plat/arm/board/fvp/fvp_bl31_setup.c \ 224 plat/arm/board/fvp/fvp_console.c \ 225 plat/arm/board/fvp/fvp_pm.c \ 226 plat/arm/board/fvp/fvp_topology.c \ 227 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 228 plat/arm/common/arm_nor_psci_mem_protect.c \ 229 ${FVP_CPU_LIBS} \ 230 ${FVP_GIC_SOURCES} \ 231 ${FVP_INTERCONNECT_SOURCES} \ 232 ${FVP_SECURITY_SOURCES} 233 234# Support for fconf in BL31 235# Added separately from the above list for better readability 236ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 237BL31_SOURCES += lib/fconf/fconf.c \ 238 lib/fconf/fconf_dyn_cfg_getter.c \ 239 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 240 241BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 242 243ifeq (${SEC_INT_DESC_IN_FCONF},1) 244BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 245endif 246 247endif 248 249ifeq (${USE_SP804_TIMER},1) 250BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 251else 252BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 253endif 254 255# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 256ifdef UNIX_MK 257FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 258FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 259 ${PLAT}_fw_config.dts \ 260 ${PLAT}_tb_fw_config.dts \ 261 ${PLAT}_soc_fw_config.dts \ 262 ${PLAT}_nt_fw_config.dts \ 263 ) 264 265FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 266FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 267FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 268FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 269 270ifeq (${SPD},tspd) 271FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 272FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 273 274# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 275$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 276endif 277 278ifeq (${SPD},spmd) 279 280ifeq ($(ARM_SPMC_MANIFEST_DTS),) 281ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 282endif 283 284FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 285FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 286 287# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 288$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 289endif 290 291# Add the FW_CONFIG to FIP and specify the same to certtool 292$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 293# Add the TB_FW_CONFIG to FIP and specify the same to certtool 294$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 295# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 296$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 297# Add the NT_FW_CONFIG to FIP and specify the same to certtool 298$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 299 300FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 301$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 302 303# Add the HW_CONFIG to FIP and specify the same to certtool 304$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 305endif 306 307# Enable Activity Monitor Unit extensions by default 308ENABLE_AMU := 1 309 310# Enable dynamic mitigation support by default 311DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 312 313ifeq (${ENABLE_AMU},1) 314BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 315 lib/cpus/aarch64/cpuamu_helpers.S 316 317ifeq (${HW_ASSISTED_COHERENCY}, 1) 318BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 319 lib/cpus/aarch64/neoverse_n1_pubsub.c 320endif 321endif 322 323ifeq (${RAS_EXTENSION},1) 324BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 325endif 326 327ifneq (${ENABLE_STACK_PROTECTOR},0) 328PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 329endif 330 331ifeq (${ARCH},aarch32) 332 NEED_BL32 := yes 333endif 334 335# Enable the dynamic translation tables library. 336ifeq ($(filter 1,${BL2_AT_EL3} ${ARM_XLAT_TABLES_LIB_V1}),) 337 ifeq (${ARCH},aarch32) 338 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 339 else # AArch64 340 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 341 endif 342endif 343 344ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 345 ifeq (${ARCH},aarch32) 346 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 347 else # AArch64 348 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 349 ifeq (${SPD},tspd) 350 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 351 endif 352 endif 353endif 354 355ifeq (${USE_DEBUGFS},1) 356 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 357endif 358 359# Add support for platform supplied linker script for BL31 build 360$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 361 362ifneq (${BL2_AT_EL3}, 0) 363 override BL1_SOURCES = 364endif 365 366# Include Measured Boot makefile before any Crypto library makefile. 367# Crypto library makefile may need default definitions of Measured Boot build 368# flags present in Measured Boot makefile. 369ifeq (${MEASURED_BOOT},1) 370 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 371 $(info Including ${RSS_MEASURED_BOOT_MK}) 372 include ${RSS_MEASURED_BOOT_MK} 373 374 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 375 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 376 endif 377 378 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 379 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 380endif 381 382include plat/arm/board/common/board_common.mk 383include plat/arm/common/arm_common.mk 384 385ifeq (${MEASURED_BOOT},1) 386BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 387 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 388 lib/psa/measured_boot.c 389 390BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 391 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 392 lib/psa/measured_boot.c 393 394PLAT_INCLUDES += -Iinclude/lib/psa 395 396# RSS is not supported on FVP right now. Thus, we use the mocked version 397# of PSA Measured Boot APIs. They return with success and hard-coded data. 398PLAT_RSS_NOT_SUPPORTED := 1 399 400endif 401 402ifeq (${TRUSTED_BOARD_BOOT}, 1) 403BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 404BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 405 406# FVP being a development platform, enable capability to disable Authentication 407# dynamically if TRUSTED_BOARD_BOOT is set. 408DYN_DISABLE_AUTH := 1 409endif 410 411# enable trace buffer control registers access to NS by default 412ENABLE_TRBE_FOR_NS := 1 413 414# enable branch record buffer control registers access in NS by default 415# only enable for aarch64 416# do not enable when ENABLE_RME=1 417ifeq (${ARCH}, aarch64) 418ifeq (${ENABLE_RME},0) 419 ENABLE_BRBE_FOR_NS := 1 420endif 421endif 422 423# enable trace system registers access to NS by default 424ENABLE_SYS_REG_TRACE_FOR_NS := 1 425 426# enable trace filter control registers access to NS by default 427ENABLE_TRF_FOR_NS := 1 428 429ifeq (${SPMC_AT_EL3}, 1) 430PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 431endif 432