1# 2# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Default cluster count for FVP 11FVP_CLUSTER_COUNT := 2 12 13# Default number of CPUs per cluster on FVP 14FVP_MAX_CPUS_PER_CLUSTER := 4 15 16# Default number of threads per CPU on FVP 17FVP_MAX_PE_PER_CPU := 1 18 19# Disable redistributor frame of inactive/fused CPU cores by marking it as read 20# only; enable redistributor frames of all CPU cores by default. 21FVP_GICR_REGION_PROTECTION := 0 22 23FVP_DT_PREFIX := fvp-base-gicv3-psci 24 25# The FVP platform depends on this macro to build with correct GIC driver. 26$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 27 28# Pass FVP_CLUSTER_COUNT to the build system. 29$(eval $(call add_define,FVP_CLUSTER_COUNT)) 30 31# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 32$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 33 34# Pass FVP_MAX_PE_PER_CPU to the build system. 35$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 36 37# Pass FVP_GICR_REGION_PROTECTION to the build system. 38$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 39 40# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 41# choose the CCI driver , else the CCN driver 42ifeq ($(FVP_CLUSTER_COUNT), 0) 43$(error "Incorrect cluster count specified for FVP port") 44else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 45FVP_INTERCONNECT_DRIVER := FVP_CCI 46else 47FVP_INTERCONNECT_DRIVER := FVP_CCN 48endif 49 50$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 51 52# Choose the GIC sources depending upon the how the FVP will be invoked 53ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 54 55# The GIC model (GIC-600 or GIC-500) will be detected at runtime 56GICV3_SUPPORT_GIC600 := 1 57GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 58 59# Include GICv3 driver files 60include drivers/arm/gic/v3/gicv3.mk 61 62FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 63 plat/common/plat_gicv3.c \ 64 plat/arm/common/arm_gicv3.c 65 66 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 67 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 68 endif 69 70else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 71 72# No GICv4 extension 73GIC_ENABLE_V4_EXTN := 0 74$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 75 76# Include GICv2 driver files 77include drivers/arm/gic/v2/gicv2.mk 78 79FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 80 plat/common/plat_gicv2.c \ 81 plat/arm/common/arm_gicv2.c 82 83FVP_DT_PREFIX := fvp-base-gicv2-psci 84else 85$(error "Incorrect GIC driver chosen on FVP port") 86endif 87 88ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 89FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 90else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 91FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 92 plat/arm/common/arm_ccn.c 93else 94$(error "Incorrect CCN driver chosen on FVP port") 95endif 96 97FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 98 plat/arm/board/fvp/fvp_security.c \ 99 plat/arm/common/arm_tzc400.c 100 101 102PLAT_INCLUDES := -Iplat/arm/board/fvp/include 103 104 105PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 106 107FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 108 109ifeq (${ARCH}, aarch64) 110 111# select a different set of CPU files, depending on whether we compile for 112# hardware assisted coherency cores or not 113ifeq (${HW_ASSISTED_COHERENCY}, 0) 114# Cores used without DSU 115 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 116 lib/cpus/aarch64/cortex_a53.S \ 117 lib/cpus/aarch64/cortex_a57.S \ 118 lib/cpus/aarch64/cortex_a72.S \ 119 lib/cpus/aarch64/cortex_a73.S 120else 121# Cores used with DSU only 122 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 123 # AArch64-only cores 124 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 125 lib/cpus/aarch64/cortex_a76ae.S \ 126 lib/cpus/aarch64/cortex_a77.S \ 127 lib/cpus/aarch64/cortex_a78.S \ 128 lib/cpus/aarch64/neoverse_n_common.S \ 129 lib/cpus/aarch64/neoverse_n1.S \ 130 lib/cpus/aarch64/neoverse_n2.S \ 131 lib/cpus/aarch64/neoverse_e1.S \ 132 lib/cpus/aarch64/neoverse_v1.S \ 133 lib/cpus/aarch64/cortex_a78_ae.S \ 134 lib/cpus/aarch64/cortex_klein.S \ 135 lib/cpus/aarch64/cortex_matterhorn.S \ 136 lib/cpus/aarch64/cortex_makalu.S \ 137 lib/cpus/aarch64/cortex_makalu_elp.S \ 138 lib/cpus/aarch64/cortex_a65.S \ 139 lib/cpus/aarch64/cortex_a65ae.S 140 endif 141 # AArch64/AArch32 cores 142 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 143 lib/cpus/aarch64/cortex_a75.S 144endif 145 146else 147FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 148endif 149 150BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 151 drivers/arm/sp805/sp805.c \ 152 drivers/delay_timer/delay_timer.c \ 153 drivers/io/io_semihosting.c \ 154 lib/semihosting/semihosting.c \ 155 lib/semihosting/${ARCH}/semihosting_call.S \ 156 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 157 plat/arm/board/fvp/fvp_bl1_setup.c \ 158 plat/arm/board/fvp/fvp_err.c \ 159 plat/arm/board/fvp/fvp_io_storage.c \ 160 ${FVP_CPU_LIBS} \ 161 ${FVP_INTERCONNECT_SOURCES} 162 163ifeq (${USE_SP804_TIMER},1) 164BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 165else 166BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 167endif 168 169 170BL2_SOURCES += drivers/arm/sp805/sp805.c \ 171 drivers/io/io_semihosting.c \ 172 lib/utils/mem_region.c \ 173 lib/semihosting/semihosting.c \ 174 lib/semihosting/${ARCH}/semihosting_call.S \ 175 plat/arm/board/fvp/fvp_bl2_setup.c \ 176 plat/arm/board/fvp/fvp_err.c \ 177 plat/arm/board/fvp/fvp_io_storage.c \ 178 plat/arm/common/arm_nor_psci_mem_protect.c \ 179 ${FVP_SECURITY_SOURCES} 180 181 182ifeq (${COT_DESC_IN_DTB},1) 183BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 184endif 185 186ifeq (${BL2_AT_EL3},1) 187BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 188 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 189 ${FVP_CPU_LIBS} \ 190 ${FVP_INTERCONNECT_SOURCES} 191endif 192 193ifeq (${USE_SP804_TIMER},1) 194BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 195endif 196 197BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 198 ${FVP_SECURITY_SOURCES} 199 200ifeq (${USE_SP804_TIMER},1) 201BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 202endif 203 204BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 205 drivers/arm/smmu/smmu_v3.c \ 206 drivers/delay_timer/delay_timer.c \ 207 drivers/cfi/v2m/v2m_flash.c \ 208 lib/utils/mem_region.c \ 209 plat/arm/board/fvp/fvp_bl31_setup.c \ 210 plat/arm/board/fvp/fvp_console.c \ 211 plat/arm/board/fvp/fvp_pm.c \ 212 plat/arm/board/fvp/fvp_topology.c \ 213 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 214 plat/arm/common/arm_nor_psci_mem_protect.c \ 215 ${FVP_CPU_LIBS} \ 216 ${FVP_GIC_SOURCES} \ 217 ${FVP_INTERCONNECT_SOURCES} \ 218 ${FVP_SECURITY_SOURCES} 219 220# Support for fconf in BL31 221# Added separately from the above list for better readability 222ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 223BL31_SOURCES += common/fdt_wrappers.c \ 224 lib/fconf/fconf.c \ 225 lib/fconf/fconf_dyn_cfg_getter.c \ 226 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 227 228ifeq (${SEC_INT_DESC_IN_FCONF},1) 229BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 230endif 231 232endif 233 234ifeq (${USE_SP804_TIMER},1) 235BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 236else 237BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 238endif 239 240# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 241ifdef UNIX_MK 242FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 243FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 244 ${PLAT}_fw_config.dts \ 245 ${PLAT}_tb_fw_config.dts \ 246 ${PLAT}_soc_fw_config.dts \ 247 ${PLAT}_nt_fw_config.dts \ 248 ) 249 250FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 251FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 252FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 253FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 254 255ifeq (${SPD},tspd) 256FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 257FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 258 259# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 260$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 261endif 262 263ifeq (${SPD},spmd) 264 265ifeq ($(ARM_SPMC_MANIFEST_DTS),) 266ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 267endif 268 269FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 270FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 271 272# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 273$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 274endif 275 276# Add the FW_CONFIG to FIP and specify the same to certtool 277$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 278# Add the TB_FW_CONFIG to FIP and specify the same to certtool 279$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 280# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 281$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 282# Add the NT_FW_CONFIG to FIP and specify the same to certtool 283$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 284 285FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 286$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 287 288# Add the HW_CONFIG to FIP and specify the same to certtool 289$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 290endif 291 292# Enable Activity Monitor Unit extensions by default 293ENABLE_AMU := 1 294 295# Enable dynamic mitigation support by default 296DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 297 298# Enable reclaiming of BL31 initialisation code for secondary cores 299# stacks for FVP. However, don't enable reclaiming for clang. 300ifneq (${RESET_TO_BL31},1) 301ifeq ($(findstring clang,$(notdir $(CC))),) 302RECLAIM_INIT_CODE := 1 303endif 304endif 305 306ifeq (${ENABLE_AMU},1) 307BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 308 lib/cpus/aarch64/cpuamu_helpers.S 309 310ifeq (${HW_ASSISTED_COHERENCY}, 1) 311BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 312 lib/cpus/aarch64/neoverse_n1_pubsub.c 313endif 314endif 315 316ifeq (${RAS_EXTENSION},1) 317BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 318endif 319 320ifneq (${ENABLE_STACK_PROTECTOR},0) 321PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 322endif 323 324ifeq (${ARCH},aarch32) 325 NEED_BL32 := yes 326endif 327 328# Enable the dynamic translation tables library. 329ifeq (${ARCH},aarch32) 330 ifeq (${RESET_TO_SP_MIN},1) 331 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 332 endif 333else # AArch64 334 ifeq (${RESET_TO_BL31},1) 335 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 336 endif 337 ifeq (${SPD},trusty) 338 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 339 endif 340endif 341 342ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 343 ifeq (${ARCH},aarch32) 344 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 345 else # AArch64 346 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 347 ifeq (${SPD},tspd) 348 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 349 endif 350 endif 351endif 352 353ifeq (${USE_DEBUGFS},1) 354 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 355endif 356 357# Add support for platform supplied linker script for BL31 build 358$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 359 360ifneq (${BL2_AT_EL3}, 0) 361 override BL1_SOURCES = 362endif 363 364include plat/arm/board/common/board_common.mk 365include plat/arm/common/arm_common.mk 366 367ifeq (${TRUSTED_BOARD_BOOT}, 1) 368BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 369BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 370 371ifeq (${MEASURED_BOOT},1) 372BL2_SOURCES += plat/arm/board/fvp/fvp_measured_boot.c 373endif 374 375# FVP being a development platform, enable capability to disable Authentication 376# dynamically if TRUSTED_BOARD_BOOT is set. 377DYN_DISABLE_AUTH := 1 378endif 379