1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34ENABLE_FEAT_AMU := 2 35ENABLE_FEAT_AMUv1p1 := 2 36ENABLE_FEAT_HCX := 2 37ENABLE_FEAT_RNG := 2 38ENABLE_FEAT_TWED := 2 39ENABLE_FEAT_GCS := 2 40 41ifeq (${ARCH}, aarch64) 42 43ifeq (${SPM_MM}, 0) 44ifeq (${CTX_INCLUDE_FPREGS}, 0) 45 ENABLE_SME_FOR_NS := 2 46 ENABLE_SME2_FOR_NS := 2 47endif 48endif 49 50 ENABLE_BRBE_FOR_NS := 2 51 ENABLE_TRBE_FOR_NS := 2 52endif 53 54ENABLE_SYS_REG_TRACE_FOR_NS := 2 55ENABLE_FEAT_CSV2_2 := 2 56ENABLE_FEAT_CSV2_3 := 2 57ENABLE_FEAT_DIT := 2 58ENABLE_FEAT_PAN := 2 59ENABLE_FEAT_VHE := 2 60CTX_INCLUDE_NEVE_REGS := 2 61ENABLE_FEAT_SEL2 := 2 62ENABLE_TRF_FOR_NS := 2 63ENABLE_FEAT_ECV := 2 64ENABLE_FEAT_FGT := 2 65ENABLE_FEAT_TCR2 := 2 66ENABLE_FEAT_S2PIE := 2 67ENABLE_FEAT_S1PIE := 2 68ENABLE_FEAT_S2POE := 2 69ENABLE_FEAT_S1POE := 2 70 71# The FVP platform depends on this macro to build with correct GIC driver. 72$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 73 74# Pass FVP_CLUSTER_COUNT to the build system. 75$(eval $(call add_define,FVP_CLUSTER_COUNT)) 76 77# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 78$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 79 80# Pass FVP_MAX_PE_PER_CPU to the build system. 81$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 82 83# Pass FVP_GICR_REGION_PROTECTION to the build system. 84$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 85 86# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 87$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 88 89# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 90# choose the CCI driver , else the CCN driver 91ifeq ($(FVP_CLUSTER_COUNT), 0) 92$(error "Incorrect cluster count specified for FVP port") 93else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 94FVP_INTERCONNECT_DRIVER := FVP_CCI 95else 96FVP_INTERCONNECT_DRIVER := FVP_CCN 97endif 98 99$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 100 101# Choose the GIC sources depending upon the how the FVP will be invoked 102ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 103 104# The GIC model (GIC-600 or GIC-500) will be detected at runtime 105GICV3_SUPPORT_GIC600 := 1 106GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 107 108# Include GICv3 driver files 109include drivers/arm/gic/v3/gicv3.mk 110 111FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 112 plat/common/plat_gicv3.c \ 113 plat/arm/common/arm_gicv3.c 114 115 ifeq ($(filter 1,${RESET_TO_BL2} \ 116 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 117 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 118 endif 119 120else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 121 122# No GICv4 extension 123GIC_ENABLE_V4_EXTN := 0 124$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 125 126# Include GICv2 driver files 127include drivers/arm/gic/v2/gicv2.mk 128 129FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 130 plat/common/plat_gicv2.c \ 131 plat/arm/common/arm_gicv2.c 132 133FVP_DT_PREFIX := fvp-base-gicv2-psci 134else 135$(error "Incorrect GIC driver chosen on FVP port") 136endif 137 138ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 139FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 140else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 141FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 142 plat/arm/common/arm_ccn.c 143else 144$(error "Incorrect CCN driver chosen on FVP port") 145endif 146 147FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 148 plat/arm/board/fvp/fvp_security.c \ 149 plat/arm/common/arm_tzc400.c 150 151 152PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 153 -Iinclude/lib/psa 154 155 156PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 157 158FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 159 160ifeq (${ARCH}, aarch64) 161 162# select a different set of CPU files, depending on whether we compile for 163# hardware assisted coherency cores or not 164ifeq (${HW_ASSISTED_COHERENCY}, 0) 165# Cores used without DSU 166 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 167 lib/cpus/aarch64/cortex_a53.S \ 168 lib/cpus/aarch64/cortex_a57.S \ 169 lib/cpus/aarch64/cortex_a72.S \ 170 lib/cpus/aarch64/cortex_a73.S 171else 172# Cores used with DSU only 173 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 174 # AArch64-only cores 175 # TODO: add all cores to the appropriate lists 176 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 177 lib/cpus/aarch64/cortex_a65ae.S \ 178 lib/cpus/aarch64/cortex_a76.S \ 179 lib/cpus/aarch64/cortex_a76ae.S \ 180 lib/cpus/aarch64/cortex_a77.S \ 181 lib/cpus/aarch64/cortex_a78.S \ 182 lib/cpus/aarch64/cortex_a78_ae.S \ 183 lib/cpus/aarch64/cortex_a78c.S \ 184 lib/cpus/aarch64/cortex_a710.S \ 185 lib/cpus/aarch64/cortex_a715.S \ 186 lib/cpus/aarch64/cortex_a720.S \ 187 lib/cpus/aarch64/neoverse_n_common.S \ 188 lib/cpus/aarch64/neoverse_n1.S \ 189 lib/cpus/aarch64/neoverse_n2.S \ 190 lib/cpus/aarch64/neoverse_v1.S \ 191 lib/cpus/aarch64/neoverse_e1.S \ 192 lib/cpus/aarch64/cortex_x2.S \ 193 lib/cpus/aarch64/cortex_x4.S \ 194 lib/cpus/aarch64/cortex_gelas.S \ 195 lib/cpus/aarch64/nevis.S \ 196 lib/cpus/aarch64/travis.S 197 endif 198 # AArch64/AArch32 cores 199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 200 lib/cpus/aarch64/cortex_a75.S 201endif 202 203else 204FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 205 lib/cpus/aarch32/cortex_a57.S \ 206 lib/cpus/aarch32/cortex_a53.S 207endif 208 209BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 210 drivers/arm/sp805/sp805.c \ 211 drivers/delay_timer/delay_timer.c \ 212 drivers/io/io_semihosting.c \ 213 lib/semihosting/semihosting.c \ 214 lib/semihosting/${ARCH}/semihosting_call.S \ 215 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 216 plat/arm/board/fvp/fvp_bl1_setup.c \ 217 plat/arm/board/fvp/fvp_err.c \ 218 plat/arm/board/fvp/fvp_io_storage.c \ 219 plat/arm/board/fvp/fvp_topology.c \ 220 ${FVP_CPU_LIBS} \ 221 ${FVP_INTERCONNECT_SOURCES} 222 223ifeq (${USE_SP804_TIMER},1) 224BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 225else 226BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 227endif 228 229 230BL2_SOURCES += drivers/arm/sp805/sp805.c \ 231 drivers/io/io_semihosting.c \ 232 lib/utils/mem_region.c \ 233 lib/semihosting/semihosting.c \ 234 lib/semihosting/${ARCH}/semihosting_call.S \ 235 plat/arm/board/fvp/fvp_bl2_setup.c \ 236 plat/arm/board/fvp/fvp_err.c \ 237 plat/arm/board/fvp/fvp_io_storage.c \ 238 plat/arm/common/arm_nor_psci_mem_protect.c \ 239 ${FVP_SECURITY_SOURCES} 240 241 242ifeq (${COT_DESC_IN_DTB},1) 243BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 244endif 245 246ifeq (${ENABLE_RME},1) 247BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 248 249BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 250 plat/arm/board/fvp/fvp_realm_attest_key.c 251endif 252 253ifeq (${ENABLE_FEAT_RNG_TRAP},1) 254BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 255endif 256 257ifeq (${RESET_TO_BL2},1) 258BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 259 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 260 ${FVP_CPU_LIBS} \ 261 ${FVP_INTERCONNECT_SOURCES} 262endif 263 264ifeq (${USE_SP804_TIMER},1) 265BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 266endif 267 268BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 269 ${FVP_SECURITY_SOURCES} 270 271ifeq (${USE_SP804_TIMER},1) 272BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 273endif 274 275BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 276 drivers/arm/smmu/smmu_v3.c \ 277 drivers/delay_timer/delay_timer.c \ 278 drivers/cfi/v2m/v2m_flash.c \ 279 lib/utils/mem_region.c \ 280 plat/arm/board/fvp/fvp_bl31_setup.c \ 281 plat/arm/board/fvp/fvp_console.c \ 282 plat/arm/board/fvp/fvp_pm.c \ 283 plat/arm/board/fvp/fvp_topology.c \ 284 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 285 plat/arm/common/arm_nor_psci_mem_protect.c \ 286 ${FVP_CPU_LIBS} \ 287 ${FVP_GIC_SOURCES} \ 288 ${FVP_INTERCONNECT_SOURCES} \ 289 ${FVP_SECURITY_SOURCES} 290 291# Support for fconf in BL31 292# Added separately from the above list for better readability 293ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 294BL31_SOURCES += lib/fconf/fconf.c \ 295 lib/fconf/fconf_dyn_cfg_getter.c \ 296 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 297 298BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 299 300ifeq (${SEC_INT_DESC_IN_FCONF},1) 301BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 302endif 303 304endif 305 306ifeq (${USE_SP804_TIMER},1) 307BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 308else 309BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 310endif 311 312ifeq (${TRANSFER_LIST}, 1) 313include lib/transfer_list/transfer_list.mk 314endif 315 316# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 317ifdef UNIX_MK 318FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 319FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 320 321FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 322$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 323 324ifeq (${TRANSFER_LIST}, 1) 325FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 326 ${PLAT}_tb_fw_config.dts \ 327 ) 328else 329FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 330 ${PLAT}_fw_config.dts \ 331 ${PLAT}_tb_fw_config.dts \ 332 ${PLAT}_soc_fw_config.dts \ 333 ${PLAT}_nt_fw_config.dts \ 334 ) 335 336FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 337FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 338FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 339 340ifeq (${SPD},tspd) 341FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 342FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 343 344# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 345$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 346endif 347 348ifeq (${SPD},spmd) 349 350ifeq ($(ARM_SPMC_MANIFEST_DTS),) 351ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 352endif 353 354FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 355FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 356 357# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 358$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 359endif 360 361# Add the FW_CONFIG to FIP and specify the same to certtool 362$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 363# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 364$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 365# Add the NT_FW_CONFIG to FIP and specify the same to certtool 366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 367endif 368 369# Add the TB_FW_CONFIG to FIP and specify the same to certtool 370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 371# Add the HW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 373endif 374 375# Enable dynamic mitigation support by default 376DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 377 378ifneq (${ENABLE_FEAT_AMU},0) 379BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 380 lib/cpus/aarch64/cpuamu_helpers.S 381 382ifeq (${HW_ASSISTED_COHERENCY}, 1) 383BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 384 lib/cpus/aarch64/neoverse_n1_pubsub.c 385endif 386endif 387 388ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 389 ifeq (${ENABLE_FEAT_RAS},1) 390 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 391 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 392 else 393 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 394 endif 395 else 396 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 397 endif 398endif 399 400ifneq (${ENABLE_STACK_PROTECTOR},0) 401PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 402endif 403 404# Enable the dynamic translation tables library. 405ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 406 ifeq (${ARCH},aarch32) 407 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 408 else # AArch64 409 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 410 endif 411endif 412 413ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 414 ifeq (${ARCH},aarch32) 415 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 416 else # AArch64 417 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 418 ifeq (${SPD},tspd) 419 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 420 endif 421 endif 422endif 423 424ifeq (${USE_DEBUGFS},1) 425 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 426endif 427 428# Add support for platform supplied linker script for BL31 build 429$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 430 431ifneq (${RESET_TO_BL2}, 0) 432 override BL1_SOURCES = 433endif 434 435include plat/arm/board/common/board_common.mk 436include plat/arm/common/arm_common.mk 437 438ifeq (${MEASURED_BOOT},1) 439BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 440 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 441 lib/psa/measured_boot.c 442 443BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 444 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 445 lib/psa/measured_boot.c 446endif 447 448ifeq (${DRTM_SUPPORT}, 1) 449BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 450 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 451 plat/arm/board/fvp/fvp_drtm_err.c \ 452 plat/arm/board/fvp/fvp_drtm_measurement.c \ 453 plat/arm/board/fvp/fvp_drtm_stub.c \ 454 plat/arm/common/arm_dyn_cfg.c \ 455 plat/arm/board/fvp/fvp_err.c 456endif 457 458ifeq (${TRUSTED_BOARD_BOOT}, 1) 459BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 460BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 461 462# FVP being a development platform, enable capability to disable Authentication 463# dynamically if TRUSTED_BOARD_BOOT is set. 464DYN_DISABLE_AUTH := 1 465endif 466 467ifeq (${SPMC_AT_EL3}, 1) 468PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 469endif 470 471PSCI_OS_INIT_MODE := 1 472 473ifeq (${SPD},spmd) 474BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 475endif 476 477# Test specific macros, keep them at bottom of this file 478$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 479ifeq (${PLATFORM_TEST_EA_FFH}, 1) 480 ifeq (${FFH_SUPPORT}, 0) 481 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 482 endif 483 484endif 485 486$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 487ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 488 ifeq (${ENABLE_FEAT_RAS}, 0) 489 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 490 endif 491 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 492 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 493 endif 494endif 495 496$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 497ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 498 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 499 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 500 endif 501 ifeq (${ENABLE_SPMD_LP}, 0) 502 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 503 endif 504 ifeq (${ENABLE_FEAT_RAS}, 0) 505 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 506 endif 507 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 508 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 509 endif 510endif 511 512ifeq (${ERRATA_ABI_SUPPORT}, 1) 513include plat/arm/board/fvp/fvp_cpu_errata.mk 514endif 515 516# Build macro necessary for running SPM tests on FVP platform 517$(eval $(call add_define,PLAT_TEST_SPM)) 518