1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. 34ifeq (${ENABLE_RME},1) 35FVP_TRUSTED_SRAM_SIZE := 384 36else 37FVP_TRUSTED_SRAM_SIZE := 256 38endif 39 40# Macro to enable helpers for running SPM tests. Disabled by default. 41PLAT_TEST_SPM := 0 42 43# By default dont build CPUs with no FVP model. 44BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 45 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96# The FVP platform depends on this macro to build with correct GIC driver. 97$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 98 99# Pass FVP_CLUSTER_COUNT to the build system. 100$(eval $(call add_define,FVP_CLUSTER_COUNT)) 101 102# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 103$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 104 105# Pass FVP_MAX_PE_PER_CPU to the build system. 106$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 107 108# Pass FVP_GICR_REGION_PROTECTION to the build system. 109$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 110 111# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 112$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 113 114# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 115# choose the CCI driver , else the CCN driver 116ifeq ($(FVP_CLUSTER_COUNT), 0) 117$(error "Incorrect cluster count specified for FVP port") 118else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 119FVP_INTERCONNECT_DRIVER := FVP_CCI 120else 121FVP_INTERCONNECT_DRIVER := FVP_CCN 122endif 123 124$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 125 126# Choose the GIC sources depending upon the how the FVP will be invoked 127ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 128 129# The GIC model (GIC-600 or GIC-500) will be detected at runtime 130GICV3_SUPPORT_GIC600 := 1 131GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 132 133# Include GICv3 driver files 134include drivers/arm/gic/v3/gicv3.mk 135 136FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 137 plat/common/plat_gicv3.c \ 138 plat/arm/common/arm_gicv3.c 139 140 ifeq ($(filter 1,${RESET_TO_BL2} \ 141 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 142 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 143 endif 144 145else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 146 147# No GICv4 extension 148GIC_ENABLE_V4_EXTN := 0 149$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 150 151# Include GICv2 driver files 152include drivers/arm/gic/v2/gicv2.mk 153 154FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 155 plat/common/plat_gicv2.c \ 156 plat/arm/common/arm_gicv2.c 157 158FVP_DT_PREFIX := fvp-base-gicv2-psci 159else 160$(error "Incorrect GIC driver chosen on FVP port") 161endif 162 163ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 164FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 165else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 166FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 167 plat/arm/common/arm_ccn.c 168else 169$(error "Incorrect CCN driver chosen on FVP port") 170endif 171 172FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 173 plat/arm/board/fvp/fvp_security.c \ 174 plat/arm/common/arm_tzc400.c 175 176 177PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 178 -Iinclude/lib/psa 179 180 181PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 182 183FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 184 185ifeq (${ARCH}, aarch64) 186 187# select a different set of CPU files, depending on whether we compile for 188# hardware assisted coherency cores or not 189ifeq (${HW_ASSISTED_COHERENCY}, 0) 190# Cores used without DSU 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 192 lib/cpus/aarch64/cortex_a53.S \ 193 lib/cpus/aarch64/cortex_a57.S \ 194 lib/cpus/aarch64/cortex_a72.S \ 195 lib/cpus/aarch64/cortex_a73.S 196else 197# Cores used with DSU only 198 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 199 # AArch64-only cores 200 # TODO: add all cores to the appropriate lists 201 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 202 lib/cpus/aarch64/cortex_a65ae.S \ 203 lib/cpus/aarch64/cortex_a76.S \ 204 lib/cpus/aarch64/cortex_a76ae.S \ 205 lib/cpus/aarch64/cortex_a77.S \ 206 lib/cpus/aarch64/cortex_a78.S \ 207 lib/cpus/aarch64/cortex_a78_ae.S \ 208 lib/cpus/aarch64/cortex_a78c.S \ 209 lib/cpus/aarch64/cortex_a710.S \ 210 lib/cpus/aarch64/cortex_a715.S \ 211 lib/cpus/aarch64/cortex_a720.S \ 212 lib/cpus/aarch64/cortex_a720_ae.S \ 213 lib/cpus/aarch64/neoverse_n_common.S \ 214 lib/cpus/aarch64/neoverse_n1.S \ 215 lib/cpus/aarch64/neoverse_n2.S \ 216 lib/cpus/aarch64/neoverse_v1.S \ 217 lib/cpus/aarch64/neoverse_e1.S \ 218 lib/cpus/aarch64/cortex_x2.S \ 219 lib/cpus/aarch64/cortex_x4.S 220 endif 221 # AArch64/AArch32 cores 222 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 223 lib/cpus/aarch64/cortex_a75.S 224endif 225 226#Include all CPUs to build to support all-errata build. 227ifeq (${ENABLE_ERRATA_ALL},1) 228 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 229 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ 230 lib/cpus/aarch64/cortex_a520.S \ 231 lib/cpus/aarch64/cortex_a725.S \ 232 lib/cpus/aarch64/cortex_x1.S \ 233 lib/cpus/aarch64/cortex_x3.S \ 234 lib/cpus/aarch64/cortex_x925.S \ 235 lib/cpus/aarch64/neoverse_n3.S \ 236 lib/cpus/aarch64/neoverse_v2.S \ 237 lib/cpus/aarch64/neoverse_v3.S 238endif 239 240#Build AArch64-only CPUs with no FVP model yet. 241ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 242 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 243 lib/cpus/aarch64/cortex_gelas.S \ 244 lib/cpus/aarch64/nevis.S \ 245 lib/cpus/aarch64/travis.S \ 246 lib/cpus/aarch64/cortex_arcadia.S \ 247 lib/cpus/aarch64/cortex_alto.S 248endif 249 250else 251FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 252 lib/cpus/aarch32/cortex_a57.S \ 253 lib/cpus/aarch32/cortex_a53.S 254endif 255 256BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 257 drivers/arm/sp805/sp805.c \ 258 drivers/delay_timer/delay_timer.c \ 259 drivers/io/io_semihosting.c \ 260 lib/semihosting/semihosting.c \ 261 lib/semihosting/${ARCH}/semihosting_call.S \ 262 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 263 plat/arm/board/fvp/fvp_bl1_setup.c \ 264 plat/arm/board/fvp/fvp_cpu_pwr.c \ 265 plat/arm/board/fvp/fvp_err.c \ 266 plat/arm/board/fvp/fvp_io_storage.c \ 267 plat/arm/board/fvp/fvp_topology.c \ 268 ${FVP_CPU_LIBS} \ 269 ${FVP_INTERCONNECT_SOURCES} 270 271ifeq (${USE_SP804_TIMER},1) 272BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 273else 274BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 275endif 276 277 278BL2_SOURCES += drivers/arm/sp805/sp805.c \ 279 drivers/io/io_semihosting.c \ 280 lib/utils/mem_region.c \ 281 lib/semihosting/semihosting.c \ 282 lib/semihosting/${ARCH}/semihosting_call.S \ 283 plat/arm/board/fvp/fvp_bl2_setup.c \ 284 plat/arm/board/fvp/fvp_err.c \ 285 plat/arm/board/fvp/fvp_io_storage.c \ 286 plat/arm/common/arm_nor_psci_mem_protect.c \ 287 ${FVP_SECURITY_SOURCES} 288 289 290ifeq (${COT_DESC_IN_DTB},1) 291BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 292endif 293 294ifeq (${ENABLE_RME},1) 295BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 296 plat/arm/board/fvp/fvp_cpu_pwr.c 297 298BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 299 plat/arm/board/fvp/fvp_realm_attest_key.c \ 300 plat/arm/board/fvp/fvp_el3_token_sign.c 301endif 302 303ifeq (${ENABLE_FEAT_RNG_TRAP},1) 304BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 305endif 306 307ifeq (${RESET_TO_BL2},1) 308BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 309 plat/arm/board/fvp/fvp_cpu_pwr.c \ 310 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 311 ${FVP_CPU_LIBS} \ 312 ${FVP_INTERCONNECT_SOURCES} 313endif 314 315ifeq (${USE_SP804_TIMER},1) 316BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 317endif 318 319BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 320 ${FVP_SECURITY_SOURCES} 321 322ifeq (${USE_SP804_TIMER},1) 323BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 324endif 325 326BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 327 drivers/arm/smmu/smmu_v3.c \ 328 drivers/delay_timer/delay_timer.c \ 329 drivers/cfi/v2m/v2m_flash.c \ 330 lib/utils/mem_region.c \ 331 plat/arm/board/fvp/fvp_bl31_setup.c \ 332 plat/arm/board/fvp/fvp_console.c \ 333 plat/arm/board/fvp/fvp_pm.c \ 334 plat/arm/board/fvp/fvp_topology.c \ 335 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 336 plat/arm/board/fvp/fvp_cpu_pwr.c \ 337 plat/arm/common/arm_nor_psci_mem_protect.c \ 338 ${FVP_CPU_LIBS} \ 339 ${FVP_GIC_SOURCES} \ 340 ${FVP_INTERCONNECT_SOURCES} \ 341 ${FVP_SECURITY_SOURCES} 342 343# Support for fconf in BL31 344# Added separately from the above list for better readability 345ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 346BL31_SOURCES += lib/fconf/fconf.c \ 347 lib/fconf/fconf_dyn_cfg_getter.c \ 348 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 349 350BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 351 352ifeq (${SEC_INT_DESC_IN_FCONF},1) 353BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 354endif 355 356endif 357 358ifeq (${USE_SP804_TIMER},1) 359BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 360else 361BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 362endif 363 364# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 365FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 366 367FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 368$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 369 370ifeq (${TRANSFER_LIST}, 0) 371FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 372 ${PLAT}_fw_config.dts \ 373 ${PLAT}_tb_fw_config.dts \ 374 ${PLAT}_soc_fw_config.dts \ 375 ${PLAT}_nt_fw_config.dts \ 376 ) 377 378FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 379FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 380FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 381FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 382 383ifeq (${SPD},tspd) 384FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 385FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 386 387# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 388$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 389endif 390 391ifeq (${SPD},spmd) 392 393ifeq ($(ARM_SPMC_MANIFEST_DTS),) 394ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 395endif 396 397FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 398FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 399 400# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 401$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 402endif 403 404# Add the FW_CONFIG to FIP and specify the same to certtool 405$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 406# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 407$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 408# Add the NT_FW_CONFIG to FIP and specify the same to certtool 409$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 410# Add the TB_FW_CONFIG to FIP and specify the same to certtool 411$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 412endif 413 414# Add the HW_CONFIG to FIP and specify the same to certtool 415$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 416 417ifeq (${TRANSFER_LIST}, 1) 418include lib/transfer_list/transfer_list.mk 419 420ifeq ($(RESET_TO_BL31), 1) 421HW_CONFIG := ${FVP_HW_CONFIG} 422FW_HANDOFF_SIZE := 20000 423 424TRANSFER_LIST_DTB_OFFSET := 0x20 425$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 426endif 427endif 428 429ifeq (${HOB_LIST}, 1) 430include lib/hob/hob.mk 431endif 432 433# Enable dynamic mitigation support by default 434DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 435 436ifneq (${ENABLE_FEAT_AMU},0) 437BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 438 lib/cpus/aarch64/cpuamu_helpers.S 439 440ifeq (${HW_ASSISTED_COHERENCY}, 1) 441BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 442 lib/cpus/aarch64/neoverse_n1_pubsub.c 443endif 444endif 445 446ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 447 ifeq (${ENABLE_FEAT_RAS},1) 448 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 449 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 450 else 451 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 452 endif 453 else 454 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 455 endif 456endif 457 458ifneq (${ENABLE_STACK_PROTECTOR},0) 459PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 460endif 461 462# Enable the dynamic translation tables library. 463ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 464 ifeq (${ARCH},aarch32) 465 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 466 else # AArch64 467 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 468 endif 469endif 470 471ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 472 ifeq (${ARCH},aarch32) 473 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 474 else # AArch64 475 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 476 ifeq (${SPD},tspd) 477 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 478 endif 479 endif 480endif 481 482ifeq (${USE_DEBUGFS},1) 483 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 484endif 485 486# Add support for platform supplied linker script for BL31 build 487$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 488 489ifneq (${RESET_TO_BL2}, 0) 490 override BL1_SOURCES = 491endif 492 493include plat/arm/board/common/board_common.mk 494include plat/arm/common/arm_common.mk 495 496ifeq (${MEASURED_BOOT},1) 497BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 498 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 499 lib/psa/measured_boot.c 500 501BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 502 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 503 lib/psa/measured_boot.c 504endif 505 506ifeq (${DRTM_SUPPORT}, 1) 507BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 508 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 509 plat/arm/board/fvp/fvp_drtm_err.c \ 510 plat/arm/board/fvp/fvp_drtm_measurement.c \ 511 plat/arm/board/fvp/fvp_drtm_stub.c \ 512 plat/arm/common/arm_dyn_cfg.c \ 513 plat/arm/board/fvp/fvp_err.c 514endif 515 516ifeq (${TRUSTED_BOARD_BOOT}, 1) 517BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 518BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 519 520# FVP being a development platform, enable capability to disable Authentication 521# dynamically if TRUSTED_BOARD_BOOT is set. 522DYN_DISABLE_AUTH := 1 523endif 524 525ifeq (${SPMC_AT_EL3}, 1) 526PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 527endif 528 529PSCI_OS_INIT_MODE := 1 530 531ifeq (${SPD},spmd) 532BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 533endif 534 535# Test specific macros, keep them at bottom of this file 536$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 537ifeq (${PLATFORM_TEST_EA_FFH}, 1) 538 ifeq (${FFH_SUPPORT}, 0) 539 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 540 endif 541 542endif 543 544$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 545ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 546 ifeq (${ENABLE_FEAT_RAS}, 0) 547 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 548 endif 549 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 550 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 551 endif 552endif 553 554$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 555ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 556 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 557 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 558 endif 559 ifeq (${ENABLE_SPMD_LP}, 0) 560 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 561 endif 562 ifeq (${ENABLE_FEAT_RAS}, 0) 563 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 564 endif 565 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 566 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 567 endif 568endif 569 570ifeq (${ERRATA_ABI_SUPPORT}, 1) 571include plat/arm/board/fvp/fvp_cpu_errata.mk 572endif 573 574# Build macro necessary for running SPM tests on FVP platform 575$(eval $(call add_define,PLAT_TEST_SPM)) 576