1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52ifeq (${ARCH},aarch64) 53ifeq (${SPM_MM}, 0) 54ifeq (${ENABLE_RME}, 0) 55ifeq (${CTX_INCLUDE_FPREGS}, 0) 56 ENABLE_SME_FOR_NS := 2 57endif 58endif 59endif 60endif 61endif 62 63# enable unconditionally for all builds 64ifeq (${ARCH}, aarch64) 65ifeq (${ENABLE_RME},0) 66 ENABLE_BRBE_FOR_NS := 2 67endif 68endif 69ENABLE_TRBE_FOR_NS := 2 70ENABLE_SYS_REG_TRACE_FOR_NS := 2 71ENABLE_FEAT_CSV2_2 := 2 72ENABLE_FEAT_PAN := 2 73ENABLE_FEAT_VHE := 2 74CTX_INCLUDE_NEVE_REGS := 2 75ENABLE_FEAT_SEL2 := 2 76ENABLE_TRF_FOR_NS := 2 77ENABLE_FEAT_ECV := 2 78ENABLE_FEAT_FGT := 2 79ENABLE_FEAT_TCR2 := 2 80ENABLE_FEAT_S2PIE := 2 81ENABLE_FEAT_S1PIE := 2 82ENABLE_FEAT_S2POE := 2 83ENABLE_FEAT_S1POE := 2 84endif 85 86# The FVP platform depends on this macro to build with correct GIC driver. 87$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 88 89# Pass FVP_CLUSTER_COUNT to the build system. 90$(eval $(call add_define,FVP_CLUSTER_COUNT)) 91 92# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 93$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 94 95# Pass FVP_MAX_PE_PER_CPU to the build system. 96$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 97 98# Pass FVP_GICR_REGION_PROTECTION to the build system. 99$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 100 101# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 102# choose the CCI driver , else the CCN driver 103ifeq ($(FVP_CLUSTER_COUNT), 0) 104$(error "Incorrect cluster count specified for FVP port") 105else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 106FVP_INTERCONNECT_DRIVER := FVP_CCI 107else 108FVP_INTERCONNECT_DRIVER := FVP_CCN 109endif 110 111$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 112 113# Choose the GIC sources depending upon the how the FVP will be invoked 114ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 115 116# The GIC model (GIC-600 or GIC-500) will be detected at runtime 117GICV3_SUPPORT_GIC600 := 1 118GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 119 120# Include GICv3 driver files 121include drivers/arm/gic/v3/gicv3.mk 122 123FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 124 plat/common/plat_gicv3.c \ 125 plat/arm/common/arm_gicv3.c 126 127 ifeq ($(filter 1,${RESET_TO_BL2} \ 128 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 129 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 130 endif 131 132else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 133 134# No GICv4 extension 135GIC_ENABLE_V4_EXTN := 0 136$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 137 138# Include GICv2 driver files 139include drivers/arm/gic/v2/gicv2.mk 140 141FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 142 plat/common/plat_gicv2.c \ 143 plat/arm/common/arm_gicv2.c 144 145FVP_DT_PREFIX := fvp-base-gicv2-psci 146else 147$(error "Incorrect GIC driver chosen on FVP port") 148endif 149 150ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 151FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 152else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 153FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 154 plat/arm/common/arm_ccn.c 155else 156$(error "Incorrect CCN driver chosen on FVP port") 157endif 158 159FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 160 plat/arm/board/fvp/fvp_security.c \ 161 plat/arm/common/arm_tzc400.c 162 163 164PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 165 -Iinclude/lib/psa 166 167 168PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 169 170FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 171 172ifeq (${ARCH}, aarch64) 173 174# select a different set of CPU files, depending on whether we compile for 175# hardware assisted coherency cores or not 176ifeq (${HW_ASSISTED_COHERENCY}, 0) 177# Cores used without DSU 178 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 179 lib/cpus/aarch64/cortex_a53.S \ 180 lib/cpus/aarch64/cortex_a57.S \ 181 lib/cpus/aarch64/cortex_a72.S \ 182 lib/cpus/aarch64/cortex_a73.S 183else 184# Cores used with DSU only 185 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 186 # AArch64-only cores 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 188 lib/cpus/aarch64/cortex_a76ae.S \ 189 lib/cpus/aarch64/cortex_a77.S \ 190 lib/cpus/aarch64/cortex_a78.S \ 191 lib/cpus/aarch64/neoverse_n_common.S \ 192 lib/cpus/aarch64/neoverse_n1.S \ 193 lib/cpus/aarch64/neoverse_n2.S \ 194 lib/cpus/aarch64/neoverse_e1.S \ 195 lib/cpus/aarch64/neoverse_v1.S \ 196 lib/cpus/aarch64/neoverse_v2.S \ 197 lib/cpus/aarch64/cortex_a78_ae.S \ 198 lib/cpus/aarch64/cortex_a510.S \ 199 lib/cpus/aarch64/cortex_a710.S \ 200 lib/cpus/aarch64/cortex_a715.S \ 201 lib/cpus/aarch64/cortex_x3.S \ 202 lib/cpus/aarch64/cortex_a65.S \ 203 lib/cpus/aarch64/cortex_a65ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_hayes.S \ 206 lib/cpus/aarch64/cortex_hunter.S \ 207 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 208 lib/cpus/aarch64/cortex_x2.S \ 209 lib/cpus/aarch64/neoverse_poseidon.S \ 210 lib/cpus/aarch64/cortex_chaberton.S \ 211 lib/cpus/aarch64/cortex_blackhawk.S 212 endif 213 # AArch64/AArch32 cores 214 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 215 lib/cpus/aarch64/cortex_a75.S 216endif 217 218else 219FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 220 lib/cpus/aarch32/cortex_a57.S 221endif 222 223BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 224 drivers/arm/sp805/sp805.c \ 225 drivers/delay_timer/delay_timer.c \ 226 drivers/io/io_semihosting.c \ 227 lib/semihosting/semihosting.c \ 228 lib/semihosting/${ARCH}/semihosting_call.S \ 229 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 230 plat/arm/board/fvp/fvp_bl1_setup.c \ 231 plat/arm/board/fvp/fvp_err.c \ 232 plat/arm/board/fvp/fvp_io_storage.c \ 233 ${FVP_CPU_LIBS} \ 234 ${FVP_INTERCONNECT_SOURCES} 235 236ifeq (${USE_SP804_TIMER},1) 237BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 238else 239BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 240endif 241 242 243BL2_SOURCES += drivers/arm/sp805/sp805.c \ 244 drivers/io/io_semihosting.c \ 245 lib/utils/mem_region.c \ 246 lib/semihosting/semihosting.c \ 247 lib/semihosting/${ARCH}/semihosting_call.S \ 248 plat/arm/board/fvp/fvp_bl2_setup.c \ 249 plat/arm/board/fvp/fvp_err.c \ 250 plat/arm/board/fvp/fvp_io_storage.c \ 251 plat/arm/common/arm_nor_psci_mem_protect.c \ 252 ${FVP_SECURITY_SOURCES} 253 254 255ifeq (${COT_DESC_IN_DTB},1) 256BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 257endif 258 259ifeq (${ENABLE_RME},1) 260BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 261 262BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 263 plat/arm/board/fvp/fvp_realm_attest_key.c 264 265# FVP platform does not support RSS, but it can leverage RSS APIs to 266# provide hardcoded token/key on request. 267BL31_SOURCES += lib/psa/delegated_attestation.c 268 269endif 270 271ifeq (${ENABLE_FEAT_RNG_TRAP},1) 272BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 273endif 274 275ifeq (${RESET_TO_BL2},1) 276BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 277 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 278 ${FVP_CPU_LIBS} \ 279 ${FVP_INTERCONNECT_SOURCES} 280endif 281 282ifeq (${USE_SP804_TIMER},1) 283BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 284endif 285 286BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 287 ${FVP_SECURITY_SOURCES} 288 289ifeq (${USE_SP804_TIMER},1) 290BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 291endif 292 293BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 294 drivers/arm/smmu/smmu_v3.c \ 295 drivers/delay_timer/delay_timer.c \ 296 drivers/cfi/v2m/v2m_flash.c \ 297 lib/utils/mem_region.c \ 298 plat/arm/board/fvp/fvp_bl31_setup.c \ 299 plat/arm/board/fvp/fvp_console.c \ 300 plat/arm/board/fvp/fvp_pm.c \ 301 plat/arm/board/fvp/fvp_topology.c \ 302 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 303 plat/arm/common/arm_nor_psci_mem_protect.c \ 304 ${FVP_CPU_LIBS} \ 305 ${FVP_GIC_SOURCES} \ 306 ${FVP_INTERCONNECT_SOURCES} \ 307 ${FVP_SECURITY_SOURCES} 308 309# Support for fconf in BL31 310# Added separately from the above list for better readability 311ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 312BL31_SOURCES += lib/fconf/fconf.c \ 313 lib/fconf/fconf_dyn_cfg_getter.c \ 314 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 315 316BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 317 318ifeq (${SEC_INT_DESC_IN_FCONF},1) 319BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 320endif 321 322endif 323 324ifeq (${USE_SP804_TIMER},1) 325BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 326else 327BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 328endif 329 330# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 331ifdef UNIX_MK 332FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 333FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 334 ${PLAT}_fw_config.dts \ 335 ${PLAT}_tb_fw_config.dts \ 336 ${PLAT}_soc_fw_config.dts \ 337 ${PLAT}_nt_fw_config.dts \ 338 ) 339 340FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 341FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 342FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 343FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 344 345ifeq (${SPD},tspd) 346FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 347FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 348 349# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 350$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 351endif 352 353ifeq (${SPD},spmd) 354 355ifeq ($(ARM_SPMC_MANIFEST_DTS),) 356ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 357endif 358 359FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 360FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 361 362# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 363$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 364endif 365 366# Add the FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 368# Add the TB_FW_CONFIG to FIP and specify the same to certtool 369$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 370# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 372# Add the NT_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 374 375FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 376$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 377 378# Add the HW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 380endif 381 382# Enable dynamic mitigation support by default 383DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 384 385ifneq (${ENABLE_FEAT_AMU},0) 386BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 387 lib/cpus/aarch64/cpuamu_helpers.S 388 389ifeq (${HW_ASSISTED_COHERENCY}, 1) 390BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 391 lib/cpus/aarch64/neoverse_n1_pubsub.c 392endif 393endif 394 395ifeq (${RAS_EXTENSION},1) 396BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 397endif 398 399ifneq (${ENABLE_STACK_PROTECTOR},0) 400PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 401endif 402 403ifeq (${ARCH},aarch32) 404 NEED_BL32 := yes 405endif 406 407# Enable the dynamic translation tables library. 408ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 409 ifeq (${ARCH},aarch32) 410 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 411 else # AArch64 412 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 413 endif 414endif 415 416ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 417 ifeq (${ARCH},aarch32) 418 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 419 else # AArch64 420 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 421 ifeq (${SPD},tspd) 422 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 423 endif 424 endif 425endif 426 427ifeq (${USE_DEBUGFS},1) 428 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 429endif 430 431# Add support for platform supplied linker script for BL31 build 432$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 433 434ifneq (${RESET_TO_BL2}, 0) 435 override BL1_SOURCES = 436endif 437 438# RSS is not supported on FVP right now. Thus, we use the mocked version 439# of the provided PSA APIs. They return with success and hard-coded token/key. 440PLAT_RSS_NOT_SUPPORTED := 1 441 442# Include Measured Boot makefile before any Crypto library makefile. 443# Crypto library makefile may need default definitions of Measured Boot build 444# flags present in Measured Boot makefile. 445ifeq (${MEASURED_BOOT},1) 446 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 447 $(info Including ${RSS_MEASURED_BOOT_MK}) 448 include ${RSS_MEASURED_BOOT_MK} 449 450 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 451 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 452 endif 453 454 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 455 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 456endif 457 458include plat/arm/board/common/board_common.mk 459include plat/arm/common/arm_common.mk 460 461ifeq (${MEASURED_BOOT},1) 462BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 463 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 464 lib/psa/measured_boot.c 465 466BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 467 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 468 lib/psa/measured_boot.c 469 470# Even though RSS is not supported on FVP (see above), we support overriding 471# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 472# the code to detect any build regressions. The resulting firmware will not be 473# functional. 474ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 475 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 476 include drivers/arm/rss/rss_comms.mk 477 BL1_SOURCES += ${RSS_COMMS_SOURCES} 478 BL2_SOURCES += ${RSS_COMMS_SOURCES} 479 BL31_SOURCES += ${RSS_COMMS_SOURCES} 480 481 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 482 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 483 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 484endif 485 486endif 487 488ifeq (${DRTM_SUPPORT}, 1) 489BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 490 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 491 plat/arm/board/fvp/fvp_drtm_err.c \ 492 plat/arm/board/fvp/fvp_drtm_measurement.c \ 493 plat/arm/board/fvp/fvp_drtm_stub.c \ 494 plat/arm/common/arm_dyn_cfg.c \ 495 plat/arm/board/fvp/fvp_err.c 496endif 497 498ifeq (${TRUSTED_BOARD_BOOT}, 1) 499BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 500BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 501 502# FVP being a development platform, enable capability to disable Authentication 503# dynamically if TRUSTED_BOARD_BOOT is set. 504DYN_DISABLE_AUTH := 1 505endif 506 507ifeq (${SPMC_AT_EL3}, 1) 508PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 509endif 510 511PSCI_OS_INIT_MODE := 1 512