1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59endif 60 61ENABLE_SYS_REG_TRACE_FOR_NS := 2 62ENABLE_FEAT_CSV2_2 := 2 63ENABLE_FEAT_CSV2_3 := 2 64ENABLE_FEAT_DEBUGV8P9 := 2 65ENABLE_FEAT_DIT := 2 66ENABLE_FEAT_PAN := 2 67ENABLE_FEAT_VHE := 2 68CTX_INCLUDE_NEVE_REGS := 2 69ENABLE_FEAT_SEL2 := 2 70ENABLE_TRF_FOR_NS := 2 71ENABLE_FEAT_ECV := 2 72ENABLE_FEAT_FGT := 2 73ENABLE_FEAT_FGT2 := 2 74ENABLE_FEAT_TCR2 := 2 75ENABLE_FEAT_S2PIE := 2 76ENABLE_FEAT_S1PIE := 2 77ENABLE_FEAT_S2POE := 2 78ENABLE_FEAT_S1POE := 2 79ENABLE_FEAT_MTE2 := 2 80 81# The FVP platform depends on this macro to build with correct GIC driver. 82$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 83 84# Pass FVP_CLUSTER_COUNT to the build system. 85$(eval $(call add_define,FVP_CLUSTER_COUNT)) 86 87# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 88$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 89 90# Pass FVP_MAX_PE_PER_CPU to the build system. 91$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 92 93# Pass FVP_GICR_REGION_PROTECTION to the build system. 94$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 95 96# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 97$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 98 99# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 100# choose the CCI driver , else the CCN driver 101ifeq ($(FVP_CLUSTER_COUNT), 0) 102$(error "Incorrect cluster count specified for FVP port") 103else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 104FVP_INTERCONNECT_DRIVER := FVP_CCI 105else 106FVP_INTERCONNECT_DRIVER := FVP_CCN 107endif 108 109$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 110 111# Choose the GIC sources depending upon the how the FVP will be invoked 112ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 113 114# The GIC model (GIC-600 or GIC-500) will be detected at runtime 115GICV3_SUPPORT_GIC600 := 1 116GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 117 118# Include GICv3 driver files 119include drivers/arm/gic/v3/gicv3.mk 120 121FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 122 plat/common/plat_gicv3.c \ 123 plat/arm/common/arm_gicv3.c 124 125 ifeq ($(filter 1,${RESET_TO_BL2} \ 126 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 127 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 128 endif 129 130else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 131 132# No GICv4 extension 133GIC_ENABLE_V4_EXTN := 0 134$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 135 136# Include GICv2 driver files 137include drivers/arm/gic/v2/gicv2.mk 138 139FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 140 plat/common/plat_gicv2.c \ 141 plat/arm/common/arm_gicv2.c 142 143FVP_DT_PREFIX := fvp-base-gicv2-psci 144else 145$(error "Incorrect GIC driver chosen on FVP port") 146endif 147 148ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 149FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 150else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 151FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 152 plat/arm/common/arm_ccn.c 153else 154$(error "Incorrect CCN driver chosen on FVP port") 155endif 156 157FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 158 plat/arm/board/fvp/fvp_security.c \ 159 plat/arm/common/arm_tzc400.c 160 161 162PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 163 -Iinclude/lib/psa 164 165 166PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 167 168FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 169 170ifeq (${ARCH}, aarch64) 171 172# select a different set of CPU files, depending on whether we compile for 173# hardware assisted coherency cores or not 174ifeq (${HW_ASSISTED_COHERENCY}, 0) 175# Cores used without DSU 176 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 177 lib/cpus/aarch64/cortex_a53.S \ 178 lib/cpus/aarch64/cortex_a57.S \ 179 lib/cpus/aarch64/cortex_a72.S \ 180 lib/cpus/aarch64/cortex_a73.S 181else 182# Cores used with DSU only 183 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 184 # AArch64-only cores 185 # TODO: add all cores to the appropriate lists 186 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 187 lib/cpus/aarch64/cortex_a65ae.S \ 188 lib/cpus/aarch64/cortex_a76.S \ 189 lib/cpus/aarch64/cortex_a76ae.S \ 190 lib/cpus/aarch64/cortex_a77.S \ 191 lib/cpus/aarch64/cortex_a78.S \ 192 lib/cpus/aarch64/cortex_a78_ae.S \ 193 lib/cpus/aarch64/cortex_a78c.S \ 194 lib/cpus/aarch64/cortex_a710.S \ 195 lib/cpus/aarch64/cortex_a715.S \ 196 lib/cpus/aarch64/cortex_a720.S \ 197 lib/cpus/aarch64/neoverse_n_common.S \ 198 lib/cpus/aarch64/neoverse_n1.S \ 199 lib/cpus/aarch64/neoverse_n2.S \ 200 lib/cpus/aarch64/neoverse_v1.S \ 201 lib/cpus/aarch64/neoverse_e1.S \ 202 lib/cpus/aarch64/cortex_x2.S \ 203 lib/cpus/aarch64/cortex_x4.S 204 endif 205 # AArch64/AArch32 cores 206 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 207 lib/cpus/aarch64/cortex_a75.S 208endif 209 210#Build AArch64-only CPUs with no FVP model yet. 211ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 212 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 213 lib/cpus/aarch64/cortex_gelas.S \ 214 lib/cpus/aarch64/nevis.S \ 215 lib/cpus/aarch64/travis.S 216endif 217 218else 219FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 220 lib/cpus/aarch32/cortex_a57.S \ 221 lib/cpus/aarch32/cortex_a53.S 222endif 223 224BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 225 drivers/arm/sp805/sp805.c \ 226 drivers/delay_timer/delay_timer.c \ 227 drivers/io/io_semihosting.c \ 228 lib/semihosting/semihosting.c \ 229 lib/semihosting/${ARCH}/semihosting_call.S \ 230 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 231 plat/arm/board/fvp/fvp_bl1_setup.c \ 232 plat/arm/board/fvp/fvp_cpu_pwr.c \ 233 plat/arm/board/fvp/fvp_err.c \ 234 plat/arm/board/fvp/fvp_io_storage.c \ 235 plat/arm/board/fvp/fvp_topology.c \ 236 ${FVP_CPU_LIBS} \ 237 ${FVP_INTERCONNECT_SOURCES} 238 239ifeq (${USE_SP804_TIMER},1) 240BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 241else 242BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 243endif 244 245 246BL2_SOURCES += drivers/arm/sp805/sp805.c \ 247 drivers/io/io_semihosting.c \ 248 lib/utils/mem_region.c \ 249 lib/semihosting/semihosting.c \ 250 lib/semihosting/${ARCH}/semihosting_call.S \ 251 plat/arm/board/fvp/fvp_bl2_setup.c \ 252 plat/arm/board/fvp/fvp_err.c \ 253 plat/arm/board/fvp/fvp_io_storage.c \ 254 plat/arm/common/arm_nor_psci_mem_protect.c \ 255 ${FVP_SECURITY_SOURCES} 256 257 258ifeq (${COT_DESC_IN_DTB},1) 259BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 260endif 261 262ifeq (${ENABLE_RME},1) 263BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 264 plat/arm/board/fvp/fvp_cpu_pwr.c 265 266BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 267 plat/arm/board/fvp/fvp_realm_attest_key.c 268endif 269 270ifeq (${ENABLE_FEAT_RNG_TRAP},1) 271BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 272endif 273 274ifeq (${RESET_TO_BL2},1) 275BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 276 plat/arm/board/fvp/fvp_cpu_pwr.c \ 277 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 278 ${FVP_CPU_LIBS} \ 279 ${FVP_INTERCONNECT_SOURCES} 280endif 281 282ifeq (${USE_SP804_TIMER},1) 283BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 284endif 285 286BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 287 ${FVP_SECURITY_SOURCES} 288 289ifeq (${USE_SP804_TIMER},1) 290BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 291endif 292 293BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 294 drivers/arm/smmu/smmu_v3.c \ 295 drivers/delay_timer/delay_timer.c \ 296 drivers/cfi/v2m/v2m_flash.c \ 297 lib/utils/mem_region.c \ 298 plat/arm/board/fvp/fvp_bl31_setup.c \ 299 plat/arm/board/fvp/fvp_console.c \ 300 plat/arm/board/fvp/fvp_pm.c \ 301 plat/arm/board/fvp/fvp_topology.c \ 302 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 303 plat/arm/board/fvp/fvp_cpu_pwr.c \ 304 plat/arm/common/arm_nor_psci_mem_protect.c \ 305 ${FVP_CPU_LIBS} \ 306 ${FVP_GIC_SOURCES} \ 307 ${FVP_INTERCONNECT_SOURCES} \ 308 ${FVP_SECURITY_SOURCES} 309 310# Support for fconf in BL31 311# Added separately from the above list for better readability 312ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 313BL31_SOURCES += lib/fconf/fconf.c \ 314 lib/fconf/fconf_dyn_cfg_getter.c \ 315 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 316 317BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 318 319ifeq (${SEC_INT_DESC_IN_FCONF},1) 320BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 321endif 322 323endif 324 325ifeq (${USE_SP804_TIMER},1) 326BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 327else 328BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 329endif 330 331# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 332ifdef UNIX_MK 333FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 334FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 335 336FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 337$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 338 339ifeq (${TRANSFER_LIST}, 1) 340FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 341 ${PLAT}_tb_fw_config.dts \ 342 ) 343else 344FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 345 ${PLAT}_fw_config.dts \ 346 ${PLAT}_tb_fw_config.dts \ 347 ${PLAT}_soc_fw_config.dts \ 348 ${PLAT}_nt_fw_config.dts \ 349 ) 350 351FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 352FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 353FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 354 355ifeq (${SPD},tspd) 356FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 357FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 358 359# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 360$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 361endif 362 363ifeq (${SPD},spmd) 364 365ifeq ($(ARM_SPMC_MANIFEST_DTS),) 366ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 367endif 368 369FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 370FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 371 372# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 374endif 375 376# Add the FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 378# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 380# Add the NT_FW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 382endif 383 384# Add the TB_FW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 386# Add the HW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 388endif 389 390ifeq (${TRANSFER_LIST}, 1) 391include lib/transfer_list/transfer_list.mk 392 393ifeq ($(RESET_TO_BL31), 1) 394HW_CONFIG := ${FVP_HW_CONFIG} 395FW_HANDOFF_SIZE := 20000 396 397TRANSFER_LIST_DTB_OFFSET := 0x20 398$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 399endif 400endif 401 402# Enable dynamic mitigation support by default 403DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 404 405ifneq (${ENABLE_FEAT_AMU},0) 406BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 407 lib/cpus/aarch64/cpuamu_helpers.S 408 409ifeq (${HW_ASSISTED_COHERENCY}, 1) 410BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 411 lib/cpus/aarch64/neoverse_n1_pubsub.c 412endif 413endif 414 415ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 416 ifeq (${ENABLE_FEAT_RAS},1) 417 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 418 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 419 else 420 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 421 endif 422 else 423 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 424 endif 425endif 426 427ifneq (${ENABLE_STACK_PROTECTOR},0) 428PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 429endif 430 431# Enable the dynamic translation tables library. 432ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 433 ifeq (${ARCH},aarch32) 434 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 435 else # AArch64 436 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 437 endif 438endif 439 440ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 441 ifeq (${ARCH},aarch32) 442 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 443 else # AArch64 444 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 445 ifeq (${SPD},tspd) 446 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 447 endif 448 endif 449endif 450 451ifeq (${USE_DEBUGFS},1) 452 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 453endif 454 455# Add support for platform supplied linker script for BL31 build 456$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 457 458ifneq (${RESET_TO_BL2}, 0) 459 override BL1_SOURCES = 460endif 461 462include plat/arm/board/common/board_common.mk 463include plat/arm/common/arm_common.mk 464 465ifeq (${MEASURED_BOOT},1) 466BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 467 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 468 lib/psa/measured_boot.c 469 470BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 471 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 472 lib/psa/measured_boot.c 473endif 474 475ifeq (${DRTM_SUPPORT}, 1) 476BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 477 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 478 plat/arm/board/fvp/fvp_drtm_err.c \ 479 plat/arm/board/fvp/fvp_drtm_measurement.c \ 480 plat/arm/board/fvp/fvp_drtm_stub.c \ 481 plat/arm/common/arm_dyn_cfg.c \ 482 plat/arm/board/fvp/fvp_err.c 483endif 484 485ifeq (${TRUSTED_BOARD_BOOT}, 1) 486BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 487BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 488 489# FVP being a development platform, enable capability to disable Authentication 490# dynamically if TRUSTED_BOARD_BOOT is set. 491DYN_DISABLE_AUTH := 1 492endif 493 494ifeq (${SPMC_AT_EL3}, 1) 495PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 496endif 497 498PSCI_OS_INIT_MODE := 1 499 500ifeq (${SPD},spmd) 501BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 502endif 503 504# Test specific macros, keep them at bottom of this file 505$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 506ifeq (${PLATFORM_TEST_EA_FFH}, 1) 507 ifeq (${FFH_SUPPORT}, 0) 508 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 509 endif 510 511endif 512 513$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 514ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 515 ifeq (${ENABLE_FEAT_RAS}, 0) 516 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 517 endif 518 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 519 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 520 endif 521endif 522 523$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 524ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 525 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 526 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 527 endif 528 ifeq (${ENABLE_SPMD_LP}, 0) 529 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 530 endif 531 ifeq (${ENABLE_FEAT_RAS}, 0) 532 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 533 endif 534 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 535 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 536 endif 537endif 538 539ifeq (${ERRATA_ABI_SUPPORT}, 1) 540include plat/arm/board/fvp/fvp_cpu_errata.mk 541endif 542 543# Build macro necessary for running SPM tests on FVP platform 544$(eval $(call add_define,PLAT_TEST_SPM)) 545