1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52 ENABLE_FEAT_GCS := 2 53ifeq (${ARCH},aarch64) 54ifeq (${SPM_MM}, 0) 55ifeq (${ENABLE_RME}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58endif 59endif 60endif 61endif 62endif 63 64# enable unconditionally for all builds 65ifeq (${ARCH}, aarch64) 66ifeq (${ENABLE_RME},0) 67 ENABLE_BRBE_FOR_NS := 2 68endif 69endif 70ENABLE_TRBE_FOR_NS := 2 71ENABLE_SYS_REG_TRACE_FOR_NS := 2 72ENABLE_FEAT_CSV2_2 := 2 73ENABLE_FEAT_DIT := 2 74ENABLE_FEAT_PAN := 2 75ENABLE_FEAT_VHE := 2 76CTX_INCLUDE_NEVE_REGS := 2 77ENABLE_FEAT_SEL2 := 2 78ENABLE_TRF_FOR_NS := 2 79ENABLE_FEAT_ECV := 2 80ENABLE_FEAT_FGT := 2 81ENABLE_FEAT_TCR2 := 2 82ENABLE_FEAT_S2PIE := 2 83ENABLE_FEAT_S1PIE := 2 84ENABLE_FEAT_S2POE := 2 85ENABLE_FEAT_S1POE := 2 86endif 87 88# The FVP platform depends on this macro to build with correct GIC driver. 89$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 90 91# Pass FVP_CLUSTER_COUNT to the build system. 92$(eval $(call add_define,FVP_CLUSTER_COUNT)) 93 94# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 95$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 96 97# Pass FVP_MAX_PE_PER_CPU to the build system. 98$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 99 100# Pass FVP_GICR_REGION_PROTECTION to the build system. 101$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 102 103# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 104# choose the CCI driver , else the CCN driver 105ifeq ($(FVP_CLUSTER_COUNT), 0) 106$(error "Incorrect cluster count specified for FVP port") 107else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 108FVP_INTERCONNECT_DRIVER := FVP_CCI 109else 110FVP_INTERCONNECT_DRIVER := FVP_CCN 111endif 112 113$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 114 115# Choose the GIC sources depending upon the how the FVP will be invoked 116ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 117 118# The GIC model (GIC-600 or GIC-500) will be detected at runtime 119GICV3_SUPPORT_GIC600 := 1 120GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 121 122# Include GICv3 driver files 123include drivers/arm/gic/v3/gicv3.mk 124 125FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 126 plat/common/plat_gicv3.c \ 127 plat/arm/common/arm_gicv3.c 128 129 ifeq ($(filter 1,${RESET_TO_BL2} \ 130 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 131 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 132 endif 133 134else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 135 136# No GICv4 extension 137GIC_ENABLE_V4_EXTN := 0 138$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 139 140# Include GICv2 driver files 141include drivers/arm/gic/v2/gicv2.mk 142 143FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 144 plat/common/plat_gicv2.c \ 145 plat/arm/common/arm_gicv2.c 146 147FVP_DT_PREFIX := fvp-base-gicv2-psci 148else 149$(error "Incorrect GIC driver chosen on FVP port") 150endif 151 152ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 153FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 154else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 155FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 156 plat/arm/common/arm_ccn.c 157else 158$(error "Incorrect CCN driver chosen on FVP port") 159endif 160 161FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 162 plat/arm/board/fvp/fvp_security.c \ 163 plat/arm/common/arm_tzc400.c 164 165 166PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 167 -Iinclude/lib/psa 168 169 170PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 171 172FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 173 174ifeq (${ARCH}, aarch64) 175 176# select a different set of CPU files, depending on whether we compile for 177# hardware assisted coherency cores or not 178ifeq (${HW_ASSISTED_COHERENCY}, 0) 179# Cores used without DSU 180 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 181 lib/cpus/aarch64/cortex_a53.S \ 182 lib/cpus/aarch64/cortex_a57.S \ 183 lib/cpus/aarch64/cortex_a72.S \ 184 lib/cpus/aarch64/cortex_a73.S 185else 186# Cores used with DSU only 187 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 188 # AArch64-only cores 189 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 190 lib/cpus/aarch64/cortex_a76ae.S \ 191 lib/cpus/aarch64/cortex_a77.S \ 192 lib/cpus/aarch64/cortex_a78.S \ 193 lib/cpus/aarch64/neoverse_n_common.S \ 194 lib/cpus/aarch64/neoverse_n1.S \ 195 lib/cpus/aarch64/neoverse_n2.S \ 196 lib/cpus/aarch64/neoverse_e1.S \ 197 lib/cpus/aarch64/neoverse_v1.S \ 198 lib/cpus/aarch64/neoverse_v2.S \ 199 lib/cpus/aarch64/cortex_a78_ae.S \ 200 lib/cpus/aarch64/cortex_a510.S \ 201 lib/cpus/aarch64/cortex_a710.S \ 202 lib/cpus/aarch64/cortex_a715.S \ 203 lib/cpus/aarch64/cortex_x3.S \ 204 lib/cpus/aarch64/cortex_a65.S \ 205 lib/cpus/aarch64/cortex_a65ae.S \ 206 lib/cpus/aarch64/cortex_a78c.S \ 207 lib/cpus/aarch64/cortex_hayes.S \ 208 lib/cpus/aarch64/cortex_hunter.S \ 209 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 210 lib/cpus/aarch64/cortex_x2.S \ 211 lib/cpus/aarch64/neoverse_poseidon.S \ 212 lib/cpus/aarch64/cortex_chaberton.S \ 213 lib/cpus/aarch64/cortex_blackhawk.S 214 endif 215 # AArch64/AArch32 cores 216 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 217 lib/cpus/aarch64/cortex_a75.S 218endif 219 220else 221FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 222 lib/cpus/aarch32/cortex_a57.S 223endif 224 225BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 226 drivers/arm/sp805/sp805.c \ 227 drivers/delay_timer/delay_timer.c \ 228 drivers/io/io_semihosting.c \ 229 lib/semihosting/semihosting.c \ 230 lib/semihosting/${ARCH}/semihosting_call.S \ 231 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 232 plat/arm/board/fvp/fvp_bl1_setup.c \ 233 plat/arm/board/fvp/fvp_err.c \ 234 plat/arm/board/fvp/fvp_io_storage.c \ 235 ${FVP_CPU_LIBS} \ 236 ${FVP_INTERCONNECT_SOURCES} 237 238ifeq (${USE_SP804_TIMER},1) 239BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 240else 241BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 242endif 243 244 245BL2_SOURCES += drivers/arm/sp805/sp805.c \ 246 drivers/io/io_semihosting.c \ 247 lib/utils/mem_region.c \ 248 lib/semihosting/semihosting.c \ 249 lib/semihosting/${ARCH}/semihosting_call.S \ 250 plat/arm/board/fvp/fvp_bl2_setup.c \ 251 plat/arm/board/fvp/fvp_err.c \ 252 plat/arm/board/fvp/fvp_io_storage.c \ 253 plat/arm/common/arm_nor_psci_mem_protect.c \ 254 ${FVP_SECURITY_SOURCES} 255 256 257ifeq (${COT_DESC_IN_DTB},1) 258BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 259endif 260 261ifeq (${ENABLE_RME},1) 262BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 263 264BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 265 plat/arm/board/fvp/fvp_realm_attest_key.c 266 267# FVP platform does not support RSS, but it can leverage RSS APIs to 268# provide hardcoded token/key on request. 269BL31_SOURCES += lib/psa/delegated_attestation.c 270 271endif 272 273ifeq (${ENABLE_FEAT_RNG_TRAP},1) 274BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 275endif 276 277ifeq (${RESET_TO_BL2},1) 278BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 279 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 280 ${FVP_CPU_LIBS} \ 281 ${FVP_INTERCONNECT_SOURCES} 282endif 283 284ifeq (${USE_SP804_TIMER},1) 285BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 286endif 287 288BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 289 ${FVP_SECURITY_SOURCES} 290 291ifeq (${USE_SP804_TIMER},1) 292BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 293endif 294 295BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 296 drivers/arm/smmu/smmu_v3.c \ 297 drivers/delay_timer/delay_timer.c \ 298 drivers/cfi/v2m/v2m_flash.c \ 299 lib/utils/mem_region.c \ 300 plat/arm/board/fvp/fvp_bl31_setup.c \ 301 plat/arm/board/fvp/fvp_console.c \ 302 plat/arm/board/fvp/fvp_pm.c \ 303 plat/arm/board/fvp/fvp_topology.c \ 304 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 305 plat/arm/common/arm_nor_psci_mem_protect.c \ 306 ${FVP_CPU_LIBS} \ 307 ${FVP_GIC_SOURCES} \ 308 ${FVP_INTERCONNECT_SOURCES} \ 309 ${FVP_SECURITY_SOURCES} 310 311# Support for fconf in BL31 312# Added separately from the above list for better readability 313ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 314BL31_SOURCES += lib/fconf/fconf.c \ 315 lib/fconf/fconf_dyn_cfg_getter.c \ 316 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 317 318BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 319 320ifeq (${SEC_INT_DESC_IN_FCONF},1) 321BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 322endif 323 324endif 325 326ifeq (${USE_SP804_TIMER},1) 327BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 328else 329BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 330endif 331 332# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 333ifdef UNIX_MK 334FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 335FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 336 ${PLAT}_fw_config.dts \ 337 ${PLAT}_tb_fw_config.dts \ 338 ${PLAT}_soc_fw_config.dts \ 339 ${PLAT}_nt_fw_config.dts \ 340 ) 341 342FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 343FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 344FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 345FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 346 347ifeq (${SPD},tspd) 348FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 349FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 350 351# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 352$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 353endif 354 355ifeq (${SPD},spmd) 356 357ifeq ($(ARM_SPMC_MANIFEST_DTS),) 358ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 359endif 360 361FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 362FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 363 364# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 366endif 367 368# Add the FW_CONFIG to FIP and specify the same to certtool 369$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 370# Add the TB_FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 372# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 374# Add the NT_FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 376 377FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 378$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 379 380# Add the HW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 382endif 383 384# Enable dynamic mitigation support by default 385DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 386 387ifneq (${ENABLE_FEAT_AMU},0) 388BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 389 lib/cpus/aarch64/cpuamu_helpers.S 390 391ifeq (${HW_ASSISTED_COHERENCY}, 1) 392BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 393 lib/cpus/aarch64/neoverse_n1_pubsub.c 394endif 395endif 396 397ifeq (${RAS_EXTENSION},1) 398BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 399endif 400 401ifneq (${ENABLE_STACK_PROTECTOR},0) 402PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 403endif 404 405ifeq (${ARCH},aarch32) 406 NEED_BL32 := yes 407endif 408 409# Enable the dynamic translation tables library. 410ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 411 ifeq (${ARCH},aarch32) 412 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 413 else # AArch64 414 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 415 endif 416endif 417 418ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 419 ifeq (${ARCH},aarch32) 420 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 421 else # AArch64 422 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 423 ifeq (${SPD},tspd) 424 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 425 endif 426 endif 427endif 428 429ifeq (${USE_DEBUGFS},1) 430 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 431endif 432 433# Add support for platform supplied linker script for BL31 build 434$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 435 436ifneq (${RESET_TO_BL2}, 0) 437 override BL1_SOURCES = 438endif 439 440# RSS is not supported on FVP right now. Thus, we use the mocked version 441# of the provided PSA APIs. They return with success and hard-coded token/key. 442PLAT_RSS_NOT_SUPPORTED := 1 443 444# Include Measured Boot makefile before any Crypto library makefile. 445# Crypto library makefile may need default definitions of Measured Boot build 446# flags present in Measured Boot makefile. 447ifeq (${MEASURED_BOOT},1) 448 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 449 $(info Including ${RSS_MEASURED_BOOT_MK}) 450 include ${RSS_MEASURED_BOOT_MK} 451 452 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 453 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 454 endif 455 456 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 457 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 458endif 459 460include plat/arm/board/common/board_common.mk 461include plat/arm/common/arm_common.mk 462 463ifeq (${MEASURED_BOOT},1) 464BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 465 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 466 lib/psa/measured_boot.c 467 468BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 469 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 470 lib/psa/measured_boot.c 471 472# Even though RSS is not supported on FVP (see above), we support overriding 473# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 474# the code to detect any build regressions. The resulting firmware will not be 475# functional. 476ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 477 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 478 include drivers/arm/rss/rss_comms.mk 479 BL1_SOURCES += ${RSS_COMMS_SOURCES} 480 BL2_SOURCES += ${RSS_COMMS_SOURCES} 481 BL31_SOURCES += ${RSS_COMMS_SOURCES} 482 483 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 484 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 485 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 486endif 487 488endif 489 490ifeq (${DRTM_SUPPORT}, 1) 491BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 492 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 493 plat/arm/board/fvp/fvp_drtm_err.c \ 494 plat/arm/board/fvp/fvp_drtm_measurement.c \ 495 plat/arm/board/fvp/fvp_drtm_stub.c \ 496 plat/arm/common/arm_dyn_cfg.c \ 497 plat/arm/board/fvp/fvp_err.c 498endif 499 500ifeq (${TRUSTED_BOARD_BOOT}, 1) 501BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 502BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 503 504# FVP being a development platform, enable capability to disable Authentication 505# dynamically if TRUSTED_BOARD_BOOT is set. 506DYN_DISABLE_AUTH := 1 507endif 508 509ifeq (${SPMC_AT_EL3}, 1) 510PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 511endif 512 513PSCI_OS_INIT_MODE := 1 514