1# 2# Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39# Enable CRC instructions via extension for ARMv8-A CPUs. 40# For ARMv8.1-A, and onwards CRC instructions are default enabled. 41ifeq (${ARM_ARCH_MAJOR},8) 42ifeq (${ARM_ARCH_MINOR},0) 43 ARM_ARCH_FEATURE := crc 44endif 45endif 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52ENABLE_FEAT_RAS := 2 53ENABLE_FEAT_SB := 2 54 55ifeq (${ARCH}, aarch64) 56 57ifeq (${SPM_MM}, 0) 58ifeq (${CTX_INCLUDE_FPREGS}, 0) 59 ENABLE_SME_FOR_NS := 2 60 ENABLE_SME2_FOR_NS := 2 61else 62 ENABLE_SVE_FOR_NS := 0 63 ENABLE_SME_FOR_NS := 0 64 ENABLE_SME2_FOR_NS := 0 65endif 66endif 67 68 ENABLE_BRBE_FOR_NS := 2 69 ENABLE_TRBE_FOR_NS := 2 70 ENABLE_FEAT_D128 := 2 71 ENABLE_FEAT_FPMR := 2 72 ENABLE_FEAT_MOPS := 2 73 ENABLE_FEAT_FGWTE3 := 2 74 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 75 ENABLE_FEAT_CPA2 := 2 76 ENABLE_FEAT_UINJ := 2 77endif 78 79ENABLE_SYS_REG_TRACE_FOR_NS := 2 80ENABLE_FEAT_CSV2_2 := 2 81ENABLE_FEAT_CSV2_3 := 2 82ENABLE_FEAT_CLRBHB := 2 83ENABLE_FEAT_DEBUGV8P9 := 2 84ENABLE_FEAT_DIT := 2 85ENABLE_FEAT_PAN := 2 86ENABLE_FEAT_VHE := 2 87CTX_INCLUDE_NEVE_REGS := 2 88ENABLE_FEAT_SEL2 := 2 89ENABLE_TRF_FOR_NS := 2 90ENABLE_FEAT_ECV := 2 91ENABLE_FEAT_FGT := 2 92ENABLE_FEAT_FGT2 := 2 93ENABLE_FEAT_THE := 2 94ENABLE_FEAT_TCR2 := 2 95ENABLE_FEAT_S2PIE := 2 96ENABLE_FEAT_S1PIE := 2 97ENABLE_FEAT_S2POE := 2 98ENABLE_FEAT_S1POE := 2 99ENABLE_FEAT_SCTLR2 := 2 100ENABLE_FEAT_MTE2 := 2 101ENABLE_FEAT_LS64_ACCDATA := 2 102ENABLE_FEAT_AIE := 2 103ENABLE_FEAT_PFAR := 2 104ENABLE_FEAT_EBEP := 2 105 106ifeq (${ENABLE_RME},1) 107 ENABLE_FEAT_MEC := 2 108 RMMD_ENABLE_IDE_KEY_PROG := 1 109endif 110 111# The FVP platform depends on this macro to build with correct GIC driver. 112$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 113 114# Pass FVP_CLUSTER_COUNT to the build system. 115$(eval $(call add_define,FVP_CLUSTER_COUNT)) 116 117# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 118$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 119 120# Pass FVP_MAX_PE_PER_CPU to the build system. 121$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 122 123# Pass FVP_GICR_REGION_PROTECTION to the build system. 124$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 125 126# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 127$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 128 129ifeq (${DRTM_SUPPORT},1) 130MBOOT_EL_HASH_ALG := sha256 131endif 132 133# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 134# choose the CCI driver , else the CCN driver 135ifeq ($(FVP_CLUSTER_COUNT), 0) 136$(error "Incorrect cluster count specified for FVP port") 137else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 138FVP_INTERCONNECT_DRIVER := FVP_CCI 139else 140FVP_INTERCONNECT_DRIVER := FVP_CCN 141endif 142 143$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 144 145ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 146include_fconf_srcs = 1 147endif 148 149ifneq ($(filter 1,${ARM_FW_CONFIG_LOAD_ENABLE} ${TRANSFER_LIST}),) 150include_fconf_srcs = 1 151endif 152 153# Choose the GIC sources depending upon the how the FVP will be invoked 154ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 155USE_GIC_DRIVER := 3 156 157# The GIC model (GIC-600 or GIC-500) will be detected at runtime 158GICV3_SUPPORT_GIC600 := 1 159GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 160 161FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 162 163ifdef include_fconf_srcs 164BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 165endif 166 167ifeq (${HW_ASSISTED_COHERENCY}, 0) 168FVP_DT_PREFIX := fvp-base-gicv3-psci 169else 170FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 171endif 172else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 173USE_GIC_DRIVER := 5 174ENABLE_FEAT_GCIE := 1 175BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 176FVP_DT_PREFIX := fvp-base-gicv5-psci 177ifneq ($(SPD),none) 178 $(error Error: GICv5 is not compatible with SPDs) 179endif 180ifeq ($(ENABLE_RME),1) 181 $(error Error: GICv5 is not compatible with RME) 182endif 183else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 184USE_GIC_DRIVER := 2 185 186# No GICv4 extension 187GIC_ENABLE_V4_EXTN := 0 188$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 189 190FVP_DT_PREFIX := fvp-base-gicv2-psci 191else 192$(error "Incorrect GIC driver chosen on FVP port") 193endif 194 195ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 196FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 197else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 198FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 199 plat/arm/common/arm_ccn.c 200else 201$(error "Incorrect CCN driver chosen on FVP port") 202endif 203 204FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 205 plat/arm/board/fvp/fvp_security.c \ 206 plat/arm/common/arm_tzc400.c 207 208 209PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 210 -Iinclude/lib/psa 211 212 213PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 214 215FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 216 217ifeq (${ARCH}, aarch64) 218 219# select a different set of CPU files, depending on whether we compile for 220# hardware assisted coherency cores or not 221ifeq (${HW_ASSISTED_COHERENCY}, 0) 222# Cores used without DSU 223 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 224 lib/cpus/aarch64/cortex_a53.S \ 225 lib/cpus/aarch64/cortex_a57.S \ 226 lib/cpus/aarch64/cortex_a72.S \ 227 lib/cpus/aarch64/cortex_a73.S 228else 229# Cores used with DSU only 230 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 231 # AArch64-only cores 232 # TODO: add all cores to the appropriate lists 233 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 234 lib/cpus/aarch64/cortex_a65ae.S \ 235 lib/cpus/aarch64/cortex_a76.S \ 236 lib/cpus/aarch64/cortex_a76ae.S \ 237 lib/cpus/aarch64/cortex_a77.S \ 238 lib/cpus/aarch64/cortex_a78.S \ 239 lib/cpus/aarch64/cortex_a78_ae.S \ 240 lib/cpus/aarch64/cortex_a78c.S \ 241 lib/cpus/aarch64/cortex_a710.S \ 242 lib/cpus/aarch64/cortex_a715.S \ 243 lib/cpus/aarch64/cortex_a720.S \ 244 lib/cpus/aarch64/cortex_a720_ae.S \ 245 lib/cpus/aarch64/neoverse_n1.S \ 246 lib/cpus/aarch64/neoverse_n2.S \ 247 lib/cpus/aarch64/neoverse_v1.S \ 248 lib/cpus/aarch64/neoverse_e1.S \ 249 lib/cpus/aarch64/cortex_x2.S \ 250 lib/cpus/aarch64/cortex_x4.S 251 endif 252 # AArch64/AArch32 cores 253 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 254 lib/cpus/aarch64/cortex_a75.S 255endif 256 257#Include all CPUs to build to support all-errata build. 258ifeq (${ENABLE_ERRATA_ALL},1) 259 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 260 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 261 lib/cpus/aarch64/cortex_a510.S \ 262 lib/cpus/aarch64/cortex_a520.S \ 263 lib/cpus/aarch64/cortex_a725.S \ 264 lib/cpus/aarch64/cortex_x1.S \ 265 lib/cpus/aarch64/cortex_x3.S \ 266 lib/cpus/aarch64/cortex_x925.S \ 267 lib/cpus/aarch64/neoverse_n3.S \ 268 lib/cpus/aarch64/neoverse_v2.S \ 269 lib/cpus/aarch64/neoverse_v3.S 270endif 271 272#Build AArch64-only CPUs with no FVP model yet. 273ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 274 ERRATA_SME_POWER_DOWN := 1 275 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 276 lib/cpus/aarch64/c1_nano.S \ 277 lib/cpus/aarch64/c1_ultra.S \ 278 lib/cpus/aarch64/c1_premium.S \ 279 lib/cpus/aarch64/canyon.S \ 280 lib/cpus/aarch64/caddo.S \ 281 lib/cpus/aarch64/rosillo.S \ 282 lib/cpus/aarch64/veymont.S \ 283 lib/cpus/aarch64/dionysus.S \ 284 lib/cpus/aarch64/venom.S \ 285 lib/cpus/aarch64/lsc25_p_core.S \ 286 lib/cpus/aarch64/lsc25_e_core.S 287endif 288 289else 290FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 291 lib/cpus/aarch32/cortex_a57.S \ 292 lib/cpus/aarch32/cortex_a53.S 293endif 294 295BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 296 drivers/arm/sp805/sp805.c \ 297 drivers/delay_timer/delay_timer.c \ 298 drivers/io/io_semihosting.c \ 299 lib/semihosting/semihosting.c \ 300 lib/semihosting/${ARCH}/semihosting_call.S \ 301 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 302 plat/arm/board/fvp/fvp_bl1_setup.c \ 303 plat/arm/board/fvp/fvp_cpu_pwr.c \ 304 plat/arm/board/fvp/fvp_err.c \ 305 plat/arm/board/fvp/fvp_io_storage.c \ 306 plat/arm/board/fvp/fvp_topology.c \ 307 ${FVP_CPU_LIBS} \ 308 ${FVP_INTERCONNECT_SOURCES} 309 310ifeq (${USE_SP804_TIMER},1) 311BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 312else 313BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 314endif 315 316 317BL2_SOURCES += drivers/arm/sp805/sp805.c \ 318 drivers/io/io_semihosting.c \ 319 lib/utils/mem_region.c \ 320 lib/semihosting/semihosting.c \ 321 lib/semihosting/${ARCH}/semihosting_call.S \ 322 plat/arm/board/fvp/fvp_bl2_setup.c \ 323 plat/arm/board/fvp/fvp_err.c \ 324 plat/arm/board/fvp/fvp_io_storage.c \ 325 plat/arm/common/arm_nor_psci_mem_protect.c \ 326 ${FVP_SECURITY_SOURCES} 327 328 329ifeq (${COT_DESC_IN_DTB},1) 330BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 331endif 332 333ifeq (${ENABLE_RME},1) 334BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 335 plat/arm/board/fvp/fvp_cpu_pwr.c 336 337BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 338 plat/arm/board/fvp/fvp_realm_attest_key.c \ 339 plat/arm/board/fvp/fvp_el3_token_sign.c \ 340 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 341 plat/arm/common/plat_rmm_mem_carveout.c 342endif 343 344ifneq (${ENABLE_FEAT_RNG_TRAP},0) 345BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 346endif 347 348ifeq (${RESET_TO_BL2},1) 349BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 350 plat/arm/board/fvp/fvp_cpu_pwr.c \ 351 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 352 ${FVP_CPU_LIBS} \ 353 ${FVP_INTERCONNECT_SOURCES} 354endif 355 356ifeq (${USE_SP804_TIMER},1) 357BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 358endif 359 360BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 361 ${FVP_SECURITY_SOURCES} 362 363ifeq (${USE_SP804_TIMER},1) 364BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 365endif 366 367BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 368 drivers/arm/smmu/smmu_v3.c \ 369 drivers/delay_timer/delay_timer.c \ 370 drivers/cfi/v2m/v2m_flash.c \ 371 lib/utils/mem_region.c \ 372 plat/arm/board/fvp/fvp_bl31_setup.c \ 373 plat/arm/board/fvp/fvp_console.c \ 374 plat/arm/board/fvp/fvp_pm.c \ 375 plat/arm/board/fvp/fvp_topology.c \ 376 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 377 plat/arm/board/fvp/fvp_cpu_pwr.c \ 378 plat/arm/common/arm_nor_psci_mem_protect.c \ 379 ${FVP_CPU_LIBS} \ 380 ${FVP_INTERCONNECT_SOURCES} \ 381 ${FVP_SECURITY_SOURCES} 382 383# Support for fconf in BL31 384# Added separately from the above list for better readability 385ifdef include_fconf_srcs 386BL31_SOURCES += lib/fconf/fconf.c \ 387 lib/fconf/fconf_dyn_cfg_getter.c \ 388 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 389 390BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 391 392ifeq (${SEC_INT_DESC_IN_FCONF},1) 393BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 394endif 395 396endif 397 398ifeq (${USE_SP804_TIMER},1) 399BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 400else 401BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 402endif 403 404# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 405FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 406 407FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 408$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 409HW_CONFIG := ${FVP_HW_CONFIG} 410 411HW_CONFIG_BASE ?= 0x82000000 412 413# Set default initrd base 128MiB offset of the default kernel address in FVP 414INITRD_BASE ?= 0x90000000 415 416# Kernel base address supports Linux kernels before v5.7 417# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 418ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 419 PRELOADED_BL33_BASE ?= 0x80080000 420 ifeq (${RESET_TO_BL31},1) 421 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 422 endif 423endif 424 425ifeq (${TRANSFER_LIST}, 0) 426FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 427 ${PLAT}_fw_config.dts \ 428 ${PLAT}_tb_fw_config.dts \ 429 ${PLAT}_soc_fw_config.dts \ 430 ${PLAT}_nt_fw_config.dts \ 431 ) 432 433FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 434FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 435FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 436FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 437 438ifeq (${SPD},tspd) 439FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 440FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 441 442# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 443$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 444endif 445 446# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 447$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 448# Add the NT_FW_CONFIG to FIP and specify the same to certtool 449$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 450endif 451 452ifeq (${SPD},spmd) 453 454ifeq ($(ARM_SPMC_MANIFEST_DTS),) 455ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 456endif 457 458FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 459FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 460 461# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 462$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 463endif 464 465# Add the HW_CONFIG to FIP and specify the same to certtool 466$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 467 468ifeq (${TRANSFER_LIST}, 1) 469 470ifeq ($(RESET_TO_BL31), 1) 471FW_HANDOFF_SIZE := 20000 472 473TRANSFER_LIST_DTB_OFFSET := 0x20 474$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 475endif 476 477# 478# To load SP_PKGs with TRANSFER_LIST, FVP_TB_FW_CONFIG is required. 479# 480ifeq (${BL2_ENABLE_SP_LOAD}, 1) 481 FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 482 ${PLAT}_tb_fw_config.dts \ 483 ) 484 485 FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 486 487 # Add the TB_FW_CONFIG to FIP and specify the same to certtool 488 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 489endif 490 491endif 492 493ifeq (${HOB_LIST}, 1) 494include lib/hob/hob.mk 495endif 496 497# Enable dynamic mitigation support by default 498DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 499 500ifneq (${ENABLE_FEAT_AMU},0) 501BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 502 lib/cpus/aarch64/cpuamu_helpers.S 503 504ifeq (${HW_ASSISTED_COHERENCY}, 1) 505BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 506 lib/cpus/aarch64/neoverse_n1_pubsub.c 507endif 508endif 509 510ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 511 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 512 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 513 endif 514 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 515 plat/arm/board/fvp/aarch64/fvp_ea.c 516endif 517 518ifneq (${ENABLE_STACK_PROTECTOR},0) 519PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 520endif 521 522# Enable the dynamic translation tables library. 523ifneq (${ARM_XLAT_TABLES_LIB_V1},1) 524 ifeq (${ARCH},aarch32) 525 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 526 else # AArch64 527 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 528 endif 529endif 530 531ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 532 ifeq (${ARCH},aarch32) 533 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 534 else # AArch64 535 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 536 ifeq (${SPD},tspd) 537 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 538 endif 539 endif 540endif 541 542ifeq (${USE_DEBUGFS},1) 543 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 544endif 545 546# Add support for platform supplied linker script for BL31 build 547PLAT_EXTRA_LD_SCRIPT := 1 548 549ifneq (${RESET_TO_BL2}, 0) 550 override BL1_SOURCES = 551endif 552 553include plat/arm/board/common/board_common.mk 554include plat/arm/common/arm_common.mk 555 556ifeq (${MEASURED_BOOT},1) 557BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 558 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 559 lib/psa/measured_boot.c \ 560 common/measured_boot_helpers.c 561 562BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 563 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 564 lib/psa/measured_boot.c \ 565 common/measured_boot_helpers.c 566endif 567 568ifeq (${DRTM_SUPPORT}, 1) 569BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 570 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 571 plat/arm/board/fvp/fvp_drtm_err.c \ 572 plat/arm/board/fvp/fvp_drtm_measurement.c \ 573 plat/arm/board/fvp/fvp_drtm_stub.c \ 574 plat/arm/common/arm_dyn_cfg.c \ 575 plat/arm/board/fvp/fvp_err.c 576endif 577 578ifeq (${TRUSTED_BOARD_BOOT}, 1) 579BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 580BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 581 582# FVP being a development platform, enable capability to disable Authentication 583# dynamically if TRUSTED_BOARD_BOOT is set. 584DYN_DISABLE_AUTH := 1 585endif 586 587ifeq (${SPMC_AT_EL3}, 1) 588PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 589endif 590 591PSCI_OS_INIT_MODE := 1 592 593ifeq (${SPD},spmd) 594BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 595endif 596 597# Test specific macros, keep them at bottom of this file 598$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 599ifeq (${PLATFORM_TEST_EA_FFH}, 1) 600 ifeq (${FFH_SUPPORT}, 0) 601 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 602 endif 603 604endif 605 606PLATFORM_TEST_RAS_FFH ?= 0 607$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 608ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 609 ifeq (${ENABLE_FEAT_RAS}, 0) 610 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 611 endif 612 ifeq (${SDEI_SUPPORT}, 0) 613 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 614 endif 615 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 616 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 617 endif 618endif 619 620$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 621ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 622 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 623 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 624 endif 625 ifeq (${ENABLE_SPMD_LP}, 0) 626 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 627 endif 628 ifeq (${ENABLE_FEAT_RAS}, 0) 629 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 630 endif 631 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 632 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 633 endif 634endif 635 636ifeq (${ERRATA_ABI_SUPPORT}, 1) 637include plat/arm/board/fvp/fvp_cpu_errata.mk 638endif 639 640# Build macro necessary for running SPM tests on FVP platform 641$(eval $(call add_define,PLAT_TEST_SPM)) 642 643ifeq (${LFA_SUPPORT},1) 644BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 645endif 646 647# This is set to 1 by default when the firmware update 648# support is enabled. Since the BL2 image is not updatable 649ifeq ($(PSA_FWU_SUPPORT),1) 650 SEPARATE_BL2_FIP := 1 651endif 652 653ifeq (${TRANSFER_LIST}, 0) 654ifeq (${SEPARATE_BL2_FIP},1) 655$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 656$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 657else 658$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 659$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 660endif 661endif 662