1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_MPAM := 2 57 ENABLE_FEAT_RNG := 2 58 ENABLE_FEAT_TWED := 2 59 ENABLE_FEAT_GCS := 2 60 ENABLE_FEAT_RAS := 2 61ifeq (${ARCH}, aarch64) 62ifneq (${SPD}, spmd) 63ifeq (${SPM_MM}, 0) 64ifeq (${CTX_INCLUDE_FPREGS}, 0) 65 ENABLE_SME_FOR_NS := 2 66 ENABLE_SME2_FOR_NS := 2 67endif 68endif 69endif 70endif 71endif 72 73# enable unconditionally for all builds 74ifeq (${ARCH}, aarch64) 75ifeq (${ENABLE_RME},0) 76 ENABLE_BRBE_FOR_NS := 2 77endif 78 ENABLE_TRBE_FOR_NS := 2 79endif 80ENABLE_SYS_REG_TRACE_FOR_NS := 2 81ENABLE_FEAT_CSV2_2 := 2 82ENABLE_FEAT_DIT := 2 83ENABLE_FEAT_PAN := 2 84ENABLE_FEAT_MTE_PERM := 2 85ENABLE_FEAT_VHE := 2 86CTX_INCLUDE_NEVE_REGS := 2 87ENABLE_FEAT_SEL2 := 2 88ENABLE_TRF_FOR_NS := 2 89ENABLE_FEAT_ECV := 2 90ENABLE_FEAT_FGT := 2 91ENABLE_FEAT_TCR2 := 2 92ENABLE_FEAT_S2PIE := 2 93ENABLE_FEAT_S1PIE := 2 94ENABLE_FEAT_S2POE := 2 95ENABLE_FEAT_S1POE := 2 96endif 97 98# The FVP platform depends on this macro to build with correct GIC driver. 99$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 100 101# Pass FVP_CLUSTER_COUNT to the build system. 102$(eval $(call add_define,FVP_CLUSTER_COUNT)) 103 104# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 105$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 106 107# Pass FVP_MAX_PE_PER_CPU to the build system. 108$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 109 110# Pass FVP_GICR_REGION_PROTECTION to the build system. 111$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 112 113# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 114$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 115 116# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 117# choose the CCI driver , else the CCN driver 118ifeq ($(FVP_CLUSTER_COUNT), 0) 119$(error "Incorrect cluster count specified for FVP port") 120else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 121FVP_INTERCONNECT_DRIVER := FVP_CCI 122else 123FVP_INTERCONNECT_DRIVER := FVP_CCN 124endif 125 126$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 127 128# Choose the GIC sources depending upon the how the FVP will be invoked 129ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 130 131# The GIC model (GIC-600 or GIC-500) will be detected at runtime 132GICV3_SUPPORT_GIC600 := 1 133GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 134 135# Include GICv3 driver files 136include drivers/arm/gic/v3/gicv3.mk 137 138FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 139 plat/common/plat_gicv3.c \ 140 plat/arm/common/arm_gicv3.c 141 142 ifeq ($(filter 1,${RESET_TO_BL2} \ 143 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 144 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 145 endif 146 147else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 148 149# No GICv4 extension 150GIC_ENABLE_V4_EXTN := 0 151$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 152 153# Include GICv2 driver files 154include drivers/arm/gic/v2/gicv2.mk 155 156FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 157 plat/common/plat_gicv2.c \ 158 plat/arm/common/arm_gicv2.c 159 160FVP_DT_PREFIX := fvp-base-gicv2-psci 161else 162$(error "Incorrect GIC driver chosen on FVP port") 163endif 164 165ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 166FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 167else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 168FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 169 plat/arm/common/arm_ccn.c 170else 171$(error "Incorrect CCN driver chosen on FVP port") 172endif 173 174FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 175 plat/arm/board/fvp/fvp_security.c \ 176 plat/arm/common/arm_tzc400.c 177 178 179PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 180 -Iinclude/lib/psa 181 182 183PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 184 185FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 186 187ifeq (${ARCH}, aarch64) 188 189# select a different set of CPU files, depending on whether we compile for 190# hardware assisted coherency cores or not 191ifeq (${HW_ASSISTED_COHERENCY}, 0) 192# Cores used without DSU 193 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 194 lib/cpus/aarch64/cortex_a53.S \ 195 lib/cpus/aarch64/cortex_a57.S \ 196 lib/cpus/aarch64/cortex_a72.S \ 197 lib/cpus/aarch64/cortex_a73.S 198else 199# Cores used with DSU only 200 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 201 # AArch64-only cores 202 # TODO: add all cores to the appropriate lists 203 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 204 lib/cpus/aarch64/cortex_a65ae.S \ 205 lib/cpus/aarch64/cortex_a76.S \ 206 lib/cpus/aarch64/cortex_a76ae.S \ 207 lib/cpus/aarch64/cortex_a77.S \ 208 lib/cpus/aarch64/cortex_a78.S \ 209 lib/cpus/aarch64/cortex_a78_ae.S \ 210 lib/cpus/aarch64/cortex_a78c.S \ 211 lib/cpus/aarch64/cortex_a710.S \ 212 lib/cpus/aarch64/neoverse_n_common.S \ 213 lib/cpus/aarch64/neoverse_n1.S \ 214 lib/cpus/aarch64/neoverse_n2.S \ 215 lib/cpus/aarch64/neoverse_v1.S \ 216 lib/cpus/aarch64/neoverse_e1.S \ 217 lib/cpus/aarch64/cortex_x2.S \ 218 lib/cpus/aarch64/cortex_gelas.S \ 219 lib/cpus/aarch64/nevis.S \ 220 lib/cpus/aarch64/travis.S 221 endif 222 # AArch64/AArch32 cores 223 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 224 lib/cpus/aarch64/cortex_a75.S 225endif 226 227else 228FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 229 lib/cpus/aarch32/cortex_a57.S \ 230 lib/cpus/aarch32/cortex_a53.S 231endif 232 233BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 234 drivers/arm/sp805/sp805.c \ 235 drivers/delay_timer/delay_timer.c \ 236 drivers/io/io_semihosting.c \ 237 lib/semihosting/semihosting.c \ 238 lib/semihosting/${ARCH}/semihosting_call.S \ 239 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 240 plat/arm/board/fvp/fvp_bl1_setup.c \ 241 plat/arm/board/fvp/fvp_err.c \ 242 plat/arm/board/fvp/fvp_io_storage.c \ 243 ${FVP_CPU_LIBS} \ 244 ${FVP_INTERCONNECT_SOURCES} 245 246ifeq (${USE_SP804_TIMER},1) 247BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 248else 249BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 250endif 251 252 253BL2_SOURCES += drivers/arm/sp805/sp805.c \ 254 drivers/io/io_semihosting.c \ 255 lib/utils/mem_region.c \ 256 lib/semihosting/semihosting.c \ 257 lib/semihosting/${ARCH}/semihosting_call.S \ 258 plat/arm/board/fvp/fvp_bl2_setup.c \ 259 plat/arm/board/fvp/fvp_err.c \ 260 plat/arm/board/fvp/fvp_io_storage.c \ 261 plat/arm/common/arm_nor_psci_mem_protect.c \ 262 ${FVP_SECURITY_SOURCES} 263 264 265ifeq (${COT_DESC_IN_DTB},1) 266BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 267endif 268 269ifeq (${ENABLE_RME},1) 270BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 271 272BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 273 plat/arm/board/fvp/fvp_realm_attest_key.c 274 275# FVP platform does not support RSS, but it can leverage RSS APIs to 276# provide hardcoded token/key on request. 277BL31_SOURCES += lib/psa/delegated_attestation.c 278 279endif 280 281ifeq (${ENABLE_FEAT_RNG_TRAP},1) 282BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 283endif 284 285ifeq (${RESET_TO_BL2},1) 286BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 287 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 288 ${FVP_CPU_LIBS} \ 289 ${FVP_INTERCONNECT_SOURCES} 290endif 291 292ifeq (${USE_SP804_TIMER},1) 293BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 294endif 295 296BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 297 ${FVP_SECURITY_SOURCES} 298 299ifeq (${USE_SP804_TIMER},1) 300BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 301endif 302 303BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 304 drivers/arm/smmu/smmu_v3.c \ 305 drivers/delay_timer/delay_timer.c \ 306 drivers/cfi/v2m/v2m_flash.c \ 307 lib/utils/mem_region.c \ 308 plat/arm/board/fvp/fvp_bl31_setup.c \ 309 plat/arm/board/fvp/fvp_console.c \ 310 plat/arm/board/fvp/fvp_pm.c \ 311 plat/arm/board/fvp/fvp_topology.c \ 312 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 313 plat/arm/common/arm_nor_psci_mem_protect.c \ 314 ${FVP_CPU_LIBS} \ 315 ${FVP_GIC_SOURCES} \ 316 ${FVP_INTERCONNECT_SOURCES} \ 317 ${FVP_SECURITY_SOURCES} 318 319# Support for fconf in BL31 320# Added separately from the above list for better readability 321ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 322BL31_SOURCES += lib/fconf/fconf.c \ 323 lib/fconf/fconf_dyn_cfg_getter.c \ 324 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 325 326BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 327 328ifeq (${SEC_INT_DESC_IN_FCONF},1) 329BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 330endif 331 332endif 333 334ifeq (${USE_SP804_TIMER},1) 335BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 336else 337BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 338endif 339 340# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 341ifdef UNIX_MK 342FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 343FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 344 ${PLAT}_fw_config.dts \ 345 ${PLAT}_tb_fw_config.dts \ 346 ${PLAT}_soc_fw_config.dts \ 347 ${PLAT}_nt_fw_config.dts \ 348 ) 349 350FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 351FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 352FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 353FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 354 355ifeq (${SPD},tspd) 356FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 357FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 358 359# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 360$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 361endif 362 363ifeq (${TRANSFER_LIST}, 1) 364include lib/transfer_list/transfer_list.mk 365endif 366 367ifeq (${SPD},spmd) 368 369ifeq ($(ARM_SPMC_MANIFEST_DTS),) 370ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 371endif 372 373FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 374FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 375 376# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 378endif 379 380# Add the FW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 382# Add the TB_FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 384# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 386# Add the NT_FW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 388 389FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 390$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 391 392# Add the HW_CONFIG to FIP and specify the same to certtool 393$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 394endif 395 396# Enable dynamic mitigation support by default 397DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 398 399ifneq (${ENABLE_FEAT_AMU},0) 400BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 401 lib/cpus/aarch64/cpuamu_helpers.S 402 403ifeq (${HW_ASSISTED_COHERENCY}, 1) 404BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 405 lib/cpus/aarch64/neoverse_n1_pubsub.c 406endif 407endif 408 409ifeq (${RAS_FFH_SUPPORT},1) 410BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 411endif 412 413ifneq (${ENABLE_STACK_PROTECTOR},0) 414PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 415endif 416 417# Enable the dynamic translation tables library. 418ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 419 ifeq (${ARCH},aarch32) 420 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 421 else # AArch64 422 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 423 endif 424endif 425 426ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 427 ifeq (${ARCH},aarch32) 428 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 429 else # AArch64 430 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 431 ifeq (${SPD},tspd) 432 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 433 endif 434 endif 435endif 436 437ifeq (${USE_DEBUGFS},1) 438 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 439endif 440 441# Add support for platform supplied linker script for BL31 build 442$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 443 444ifneq (${RESET_TO_BL2}, 0) 445 override BL1_SOURCES = 446endif 447 448# RSS is not supported on FVP right now. Thus, we use the mocked version 449# of the provided PSA APIs. They return with success and hard-coded token/key. 450PLAT_RSS_NOT_SUPPORTED := 1 451 452# Include Measured Boot makefile before any Crypto library makefile. 453# Crypto library makefile may need default definitions of Measured Boot build 454# flags present in Measured Boot makefile. 455ifeq (${MEASURED_BOOT},1) 456 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 457 $(info Including ${RSS_MEASURED_BOOT_MK}) 458 include ${RSS_MEASURED_BOOT_MK} 459 460 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 461 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 462 endif 463 464 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 465 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 466endif 467 468include plat/arm/board/common/board_common.mk 469include plat/arm/common/arm_common.mk 470 471ifeq (${MEASURED_BOOT},1) 472BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 473 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 474 lib/psa/measured_boot.c 475 476BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 477 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 478 lib/psa/measured_boot.c 479 480# Even though RSS is not supported on FVP (see above), we support overriding 481# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 482# the code to detect any build regressions. The resulting firmware will not be 483# functional. 484ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 485 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 486 include drivers/arm/rss/rss_comms.mk 487 BL1_SOURCES += ${RSS_COMMS_SOURCES} 488 BL2_SOURCES += ${RSS_COMMS_SOURCES} 489 BL31_SOURCES += ${RSS_COMMS_SOURCES} 490 491 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 492 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 493 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 494endif 495 496endif 497 498ifeq (${DRTM_SUPPORT}, 1) 499BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 500 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 501 plat/arm/board/fvp/fvp_drtm_err.c \ 502 plat/arm/board/fvp/fvp_drtm_measurement.c \ 503 plat/arm/board/fvp/fvp_drtm_stub.c \ 504 plat/arm/common/arm_dyn_cfg.c \ 505 plat/arm/board/fvp/fvp_err.c 506endif 507 508ifeq (${TRUSTED_BOARD_BOOT}, 1) 509BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 510BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 511 512# FVP being a development platform, enable capability to disable Authentication 513# dynamically if TRUSTED_BOARD_BOOT is set. 514DYN_DISABLE_AUTH := 1 515endif 516 517ifeq (${SPMC_AT_EL3}, 1) 518PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 519endif 520 521PSCI_OS_INIT_MODE := 1 522 523ifeq (${SPD},spmd) 524BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 525endif 526 527# Test specific macros, keep them at bottom of this file 528$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 529ifeq (${PLATFORM_TEST_EA_FFH}, 1) 530 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 531 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 532 endif 533BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 534endif 535 536$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 537ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 538 ifeq (${RAS_EXTENSION}, 0) 539 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 540 endif 541endif 542 543ifeq (${ERRATA_ABI_SUPPORT}, 1) 544include plat/arm/board/fvp/fvp_cpu_errata.mk 545endif 546 547# Build macro necessary for running SPM tests on FVP platform 548$(eval $(call add_define,PLAT_TEST_SPM)) 549