1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. 34ifeq (${ENABLE_RME},1) 35FVP_TRUSTED_SRAM_SIZE := 384 36else 37FVP_TRUSTED_SRAM_SIZE := 256 38endif 39 40# Macro to enable helpers for running SPM tests. Disabled by default. 41PLAT_TEST_SPM := 0 42 43# By default dont build CPUs with no FVP model. 44BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 45 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96ifeq (${ENABLE_RME},1) 97 ENABLE_FEAT_MEC := 2 98 RMMD_ENABLE_IDE_KEY_PROG := 1 99endif 100 101# The FVP platform depends on this macro to build with correct GIC driver. 102$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 103 104# Pass FVP_CLUSTER_COUNT to the build system. 105$(eval $(call add_define,FVP_CLUSTER_COUNT)) 106 107# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 108$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 109 110# Pass FVP_MAX_PE_PER_CPU to the build system. 111$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 112 113# Pass FVP_GICR_REGION_PROTECTION to the build system. 114$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 115 116# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 117$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 118 119# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 120# choose the CCI driver , else the CCN driver 121ifeq ($(FVP_CLUSTER_COUNT), 0) 122$(error "Incorrect cluster count specified for FVP port") 123else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 124FVP_INTERCONNECT_DRIVER := FVP_CCI 125else 126FVP_INTERCONNECT_DRIVER := FVP_CCN 127endif 128 129$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 130 131# Choose the GIC sources depending upon the how the FVP will be invoked 132ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 133USE_GIC_DRIVER := 3 134 135# The GIC model (GIC-600 or GIC-500) will be detected at runtime 136GICV3_SUPPORT_GIC600 := 1 137GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 138 139FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 140 141else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 142USE_GIC_DRIVER := 2 143 144# No GICv4 extension 145GIC_ENABLE_V4_EXTN := 0 146$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 147 148FVP_DT_PREFIX := fvp-base-gicv2-psci 149else 150$(error "Incorrect GIC driver chosen on FVP port") 151endif 152 153ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 154FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 155else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 156FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 157 plat/arm/common/arm_ccn.c 158else 159$(error "Incorrect CCN driver chosen on FVP port") 160endif 161 162FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 163 plat/arm/board/fvp/fvp_security.c \ 164 plat/arm/common/arm_tzc400.c 165 166 167PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 168 -Iinclude/lib/psa 169 170 171PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 172 173FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 174 175ifeq (${ARCH}, aarch64) 176 177# select a different set of CPU files, depending on whether we compile for 178# hardware assisted coherency cores or not 179ifeq (${HW_ASSISTED_COHERENCY}, 0) 180# Cores used without DSU 181 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 182 lib/cpus/aarch64/cortex_a53.S \ 183 lib/cpus/aarch64/cortex_a57.S \ 184 lib/cpus/aarch64/cortex_a72.S \ 185 lib/cpus/aarch64/cortex_a73.S 186else 187# Cores used with DSU only 188 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 189 # AArch64-only cores 190 # TODO: add all cores to the appropriate lists 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 192 lib/cpus/aarch64/cortex_a65ae.S \ 193 lib/cpus/aarch64/cortex_a76.S \ 194 lib/cpus/aarch64/cortex_a76ae.S \ 195 lib/cpus/aarch64/cortex_a77.S \ 196 lib/cpus/aarch64/cortex_a78.S \ 197 lib/cpus/aarch64/cortex_a78_ae.S \ 198 lib/cpus/aarch64/cortex_a78c.S \ 199 lib/cpus/aarch64/cortex_a710.S \ 200 lib/cpus/aarch64/cortex_a715.S \ 201 lib/cpus/aarch64/cortex_a720.S \ 202 lib/cpus/aarch64/cortex_a720_ae.S \ 203 lib/cpus/aarch64/neoverse_n1.S \ 204 lib/cpus/aarch64/neoverse_n2.S \ 205 lib/cpus/aarch64/neoverse_v1.S \ 206 lib/cpus/aarch64/neoverse_e1.S \ 207 lib/cpus/aarch64/cortex_x2.S \ 208 lib/cpus/aarch64/cortex_x4.S 209 endif 210 # AArch64/AArch32 cores 211 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 212 lib/cpus/aarch64/cortex_a75.S 213endif 214 215#Include all CPUs to build to support all-errata build. 216ifeq (${ENABLE_ERRATA_ALL},1) 217 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 219 lib/cpus/aarch64/cortex_a510.S \ 220 lib/cpus/aarch64/cortex_a520.S \ 221 lib/cpus/aarch64/cortex_a725.S \ 222 lib/cpus/aarch64/cortex_x1.S \ 223 lib/cpus/aarch64/cortex_x3.S \ 224 lib/cpus/aarch64/cortex_x925.S \ 225 lib/cpus/aarch64/neoverse_n3.S \ 226 lib/cpus/aarch64/neoverse_v2.S \ 227 lib/cpus/aarch64/neoverse_v3.S 228endif 229 230#Build AArch64-only CPUs with no FVP model yet. 231ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 232 # travis/gelas need these 233 FEAT_PABANDON := 1 234 ERRATA_SME_POWER_DOWN := 1 235 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 236 lib/cpus/aarch64/nevis.S \ 237 lib/cpus/aarch64/travis.S \ 238 lib/cpus/aarch64/cortex_alto.S 239endif 240 241else 242FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 243 lib/cpus/aarch32/cortex_a57.S \ 244 lib/cpus/aarch32/cortex_a53.S 245endif 246 247BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 248 drivers/arm/sp805/sp805.c \ 249 drivers/delay_timer/delay_timer.c \ 250 drivers/io/io_semihosting.c \ 251 lib/semihosting/semihosting.c \ 252 lib/semihosting/${ARCH}/semihosting_call.S \ 253 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 254 plat/arm/board/fvp/fvp_bl1_setup.c \ 255 plat/arm/board/fvp/fvp_cpu_pwr.c \ 256 plat/arm/board/fvp/fvp_err.c \ 257 plat/arm/board/fvp/fvp_io_storage.c \ 258 plat/arm/board/fvp/fvp_topology.c \ 259 ${FVP_CPU_LIBS} \ 260 ${FVP_INTERCONNECT_SOURCES} 261 262ifeq (${USE_SP804_TIMER},1) 263BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 264else 265BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 266endif 267 268 269BL2_SOURCES += drivers/arm/sp805/sp805.c \ 270 drivers/io/io_semihosting.c \ 271 lib/utils/mem_region.c \ 272 lib/semihosting/semihosting.c \ 273 lib/semihosting/${ARCH}/semihosting_call.S \ 274 plat/arm/board/fvp/fvp_bl2_setup.c \ 275 plat/arm/board/fvp/fvp_err.c \ 276 plat/arm/board/fvp/fvp_io_storage.c \ 277 plat/arm/common/arm_nor_psci_mem_protect.c \ 278 ${FVP_SECURITY_SOURCES} 279 280 281ifeq (${COT_DESC_IN_DTB},1) 282BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 283endif 284 285ifeq (${ENABLE_RME},1) 286BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 287 plat/arm/board/fvp/fvp_cpu_pwr.c 288 289BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 290 plat/arm/board/fvp/fvp_realm_attest_key.c \ 291 plat/arm/board/fvp/fvp_el3_token_sign.c \ 292 plat/arm/board/fvp/fvp_ide_keymgmt.c 293endif 294 295ifneq (${ENABLE_FEAT_RNG_TRAP},0) 296BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 297endif 298 299ifeq (${RESET_TO_BL2},1) 300BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 301 plat/arm/board/fvp/fvp_cpu_pwr.c \ 302 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 303 ${FVP_CPU_LIBS} \ 304 ${FVP_INTERCONNECT_SOURCES} 305endif 306 307ifeq (${USE_SP804_TIMER},1) 308BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 309endif 310 311BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 312 ${FVP_SECURITY_SOURCES} 313 314ifeq (${USE_SP804_TIMER},1) 315BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 316endif 317 318BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 319 drivers/arm/smmu/smmu_v3.c \ 320 drivers/delay_timer/delay_timer.c \ 321 drivers/cfi/v2m/v2m_flash.c \ 322 lib/utils/mem_region.c \ 323 plat/arm/board/fvp/fvp_bl31_setup.c \ 324 plat/arm/board/fvp/fvp_console.c \ 325 plat/arm/board/fvp/fvp_pm.c \ 326 plat/arm/board/fvp/fvp_topology.c \ 327 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 328 plat/arm/board/fvp/fvp_cpu_pwr.c \ 329 plat/arm/common/arm_nor_psci_mem_protect.c \ 330 ${FVP_CPU_LIBS} \ 331 ${FVP_INTERCONNECT_SOURCES} \ 332 ${FVP_SECURITY_SOURCES} 333 334# Support for fconf in BL31 335# Added separately from the above list for better readability 336ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 337BL31_SOURCES += lib/fconf/fconf.c \ 338 lib/fconf/fconf_dyn_cfg_getter.c \ 339 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 340 341BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 342 343ifeq (${SEC_INT_DESC_IN_FCONF},1) 344BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 345endif 346 347endif 348 349ifeq (${USE_SP804_TIMER},1) 350BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 351else 352BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 353endif 354 355# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 356FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 357 358FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 359$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 360HW_CONFIG := ${FVP_HW_CONFIG} 361 362# Allow hw_config's secondary-load-address in the DT to be changed 363FVP_HW_CONFIG_ADDR ?= 0x82000000 364DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR) 365 366# Set default initrd base 128MiB offset of the default kernel address in FVP 367INITRD_BASE ?= 0x90000000 368 369# Kernel base address supports Linux kernels before v5.7 370# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 371ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 372 PRELOADED_BL33_BASE ?= 0x80080000 373 ifeq (${RESET_TO_BL31},1) 374 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 375 endif 376endif 377 378ifeq (${TRANSFER_LIST}, 0) 379FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 380 ${PLAT}_fw_config.dts \ 381 ${PLAT}_tb_fw_config.dts \ 382 ${PLAT}_soc_fw_config.dts \ 383 ${PLAT}_nt_fw_config.dts \ 384 ) 385 386FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 387FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 388FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 389FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 390 391ifeq (${SPD},tspd) 392FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 393FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 394 395# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 396$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 397endif 398 399ifeq (${SPD},spmd) 400 401ifeq ($(ARM_SPMC_MANIFEST_DTS),) 402ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 403endif 404 405FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 406FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 407 408# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 409$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 410endif 411 412# Add the FW_CONFIG to FIP and specify the same to certtool 413$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 414# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 415$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 416# Add the NT_FW_CONFIG to FIP and specify the same to certtool 417$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 418# Add the TB_FW_CONFIG to FIP and specify the same to certtool 419$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 420endif 421 422# Add the HW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 424 425ifeq (${TRANSFER_LIST}, 1) 426 427ifeq ($(RESET_TO_BL31), 1) 428FW_HANDOFF_SIZE := 20000 429 430TRANSFER_LIST_DTB_OFFSET := 0x20 431$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 432endif 433endif 434 435ifeq (${HOB_LIST}, 1) 436include lib/hob/hob.mk 437endif 438 439# Enable dynamic mitigation support by default 440DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 441 442ifneq (${ENABLE_FEAT_AMU},0) 443BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 444 lib/cpus/aarch64/cpuamu_helpers.S 445 446ifeq (${HW_ASSISTED_COHERENCY}, 1) 447BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 448 lib/cpus/aarch64/neoverse_n1_pubsub.c 449endif 450endif 451 452ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 453 ifeq (${ENABLE_FEAT_RAS},1) 454 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 455 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 456 else 457 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 458 endif 459 else 460 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 461 endif 462endif 463 464ifneq (${ENABLE_STACK_PROTECTOR},0) 465PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 466endif 467 468# Enable the dynamic translation tables library. 469ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 470 ifeq (${ARCH},aarch32) 471 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 472 else # AArch64 473 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 474 endif 475endif 476 477ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 478 ifeq (${ARCH},aarch32) 479 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 480 else # AArch64 481 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 482 ifeq (${SPD},tspd) 483 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 484 endif 485 endif 486endif 487 488ifeq (${USE_DEBUGFS},1) 489 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 490endif 491 492# Add support for platform supplied linker script for BL31 build 493$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 494 495ifneq (${RESET_TO_BL2}, 0) 496 override BL1_SOURCES = 497endif 498 499include plat/arm/board/common/board_common.mk 500include plat/arm/common/arm_common.mk 501 502ifeq (${MEASURED_BOOT},1) 503BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 504 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 505 lib/psa/measured_boot.c 506 507BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 508 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 509 lib/psa/measured_boot.c 510endif 511 512ifeq (${DRTM_SUPPORT}, 1) 513BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 514 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 515 plat/arm/board/fvp/fvp_drtm_err.c \ 516 plat/arm/board/fvp/fvp_drtm_measurement.c \ 517 plat/arm/board/fvp/fvp_drtm_stub.c \ 518 plat/arm/common/arm_dyn_cfg.c \ 519 plat/arm/board/fvp/fvp_err.c 520endif 521 522ifeq (${TRUSTED_BOARD_BOOT}, 1) 523BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 524BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 525 526# FVP being a development platform, enable capability to disable Authentication 527# dynamically if TRUSTED_BOARD_BOOT is set. 528DYN_DISABLE_AUTH := 1 529endif 530 531ifeq (${SPMC_AT_EL3}, 1) 532PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 533endif 534 535PSCI_OS_INIT_MODE := 1 536 537ifeq (${SPD},spmd) 538BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 539endif 540 541# Test specific macros, keep them at bottom of this file 542$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 543ifeq (${PLATFORM_TEST_EA_FFH}, 1) 544 ifeq (${FFH_SUPPORT}, 0) 545 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 546 endif 547 548endif 549 550$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 551ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 552 ifeq (${ENABLE_FEAT_RAS}, 0) 553 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 554 endif 555 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 556 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 557 endif 558endif 559 560$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 561ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 562 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 563 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 564 endif 565 ifeq (${ENABLE_SPMD_LP}, 0) 566 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 567 endif 568 ifeq (${ENABLE_FEAT_RAS}, 0) 569 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 570 endif 571 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 572 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 573 endif 574endif 575 576ifeq (${ERRATA_ABI_SUPPORT}, 1) 577include plat/arm/board/fvp/fvp_cpu_errata.mk 578endif 579 580# Build macro necessary for running SPM tests on FVP platform 581$(eval $(call add_define,PLAT_TEST_SPM)) 582