1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59endif 60 61ENABLE_SYS_REG_TRACE_FOR_NS := 2 62ENABLE_FEAT_CSV2_2 := 2 63ENABLE_FEAT_CSV2_3 := 2 64ENABLE_FEAT_DEBUGV8P9 := 2 65ENABLE_FEAT_DIT := 2 66ENABLE_FEAT_PAN := 2 67ENABLE_FEAT_VHE := 2 68CTX_INCLUDE_NEVE_REGS := 2 69ENABLE_FEAT_SEL2 := 2 70ENABLE_TRF_FOR_NS := 2 71ENABLE_FEAT_ECV := 2 72ENABLE_FEAT_FGT := 2 73ENABLE_FEAT_FGT2 := 2 74ENABLE_FEAT_TCR2 := 2 75ENABLE_FEAT_S2PIE := 2 76ENABLE_FEAT_S1PIE := 2 77ENABLE_FEAT_S2POE := 2 78ENABLE_FEAT_S1POE := 2 79 80# The FVP platform depends on this macro to build with correct GIC driver. 81$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 82 83# Pass FVP_CLUSTER_COUNT to the build system. 84$(eval $(call add_define,FVP_CLUSTER_COUNT)) 85 86# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 87$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 88 89# Pass FVP_MAX_PE_PER_CPU to the build system. 90$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 91 92# Pass FVP_GICR_REGION_PROTECTION to the build system. 93$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 94 95# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 96$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 97 98# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 99# choose the CCI driver , else the CCN driver 100ifeq ($(FVP_CLUSTER_COUNT), 0) 101$(error "Incorrect cluster count specified for FVP port") 102else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 103FVP_INTERCONNECT_DRIVER := FVP_CCI 104else 105FVP_INTERCONNECT_DRIVER := FVP_CCN 106endif 107 108$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 109 110# Choose the GIC sources depending upon the how the FVP will be invoked 111ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 112 113# The GIC model (GIC-600 or GIC-500) will be detected at runtime 114GICV3_SUPPORT_GIC600 := 1 115GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 116 117# Include GICv3 driver files 118include drivers/arm/gic/v3/gicv3.mk 119 120FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 121 plat/common/plat_gicv3.c \ 122 plat/arm/common/arm_gicv3.c 123 124 ifeq ($(filter 1,${RESET_TO_BL2} \ 125 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 126 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 127 endif 128 129else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 130 131# No GICv4 extension 132GIC_ENABLE_V4_EXTN := 0 133$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 134 135# Include GICv2 driver files 136include drivers/arm/gic/v2/gicv2.mk 137 138FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 139 plat/common/plat_gicv2.c \ 140 plat/arm/common/arm_gicv2.c 141 142FVP_DT_PREFIX := fvp-base-gicv2-psci 143else 144$(error "Incorrect GIC driver chosen on FVP port") 145endif 146 147ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 148FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 149else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 150FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 151 plat/arm/common/arm_ccn.c 152else 153$(error "Incorrect CCN driver chosen on FVP port") 154endif 155 156FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 157 plat/arm/board/fvp/fvp_security.c \ 158 plat/arm/common/arm_tzc400.c 159 160 161PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 162 -Iinclude/lib/psa 163 164 165PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 166 167FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 168 169ifeq (${ARCH}, aarch64) 170 171# select a different set of CPU files, depending on whether we compile for 172# hardware assisted coherency cores or not 173ifeq (${HW_ASSISTED_COHERENCY}, 0) 174# Cores used without DSU 175 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 176 lib/cpus/aarch64/cortex_a53.S \ 177 lib/cpus/aarch64/cortex_a57.S \ 178 lib/cpus/aarch64/cortex_a72.S \ 179 lib/cpus/aarch64/cortex_a73.S 180else 181# Cores used with DSU only 182 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 183 # AArch64-only cores 184 # TODO: add all cores to the appropriate lists 185 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 186 lib/cpus/aarch64/cortex_a65ae.S \ 187 lib/cpus/aarch64/cortex_a76.S \ 188 lib/cpus/aarch64/cortex_a76ae.S \ 189 lib/cpus/aarch64/cortex_a77.S \ 190 lib/cpus/aarch64/cortex_a78.S \ 191 lib/cpus/aarch64/cortex_a78_ae.S \ 192 lib/cpus/aarch64/cortex_a78c.S \ 193 lib/cpus/aarch64/cortex_a710.S \ 194 lib/cpus/aarch64/cortex_a715.S \ 195 lib/cpus/aarch64/cortex_a720.S \ 196 lib/cpus/aarch64/neoverse_n_common.S \ 197 lib/cpus/aarch64/neoverse_n1.S \ 198 lib/cpus/aarch64/neoverse_n2.S \ 199 lib/cpus/aarch64/neoverse_v1.S \ 200 lib/cpus/aarch64/neoverse_e1.S \ 201 lib/cpus/aarch64/cortex_x2.S \ 202 lib/cpus/aarch64/cortex_x4.S 203 endif 204 # AArch64/AArch32 cores 205 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 206 lib/cpus/aarch64/cortex_a75.S 207endif 208 209#Build AArch64-only CPUs with no FVP model yet. 210ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 211 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 212 lib/cpus/aarch64/cortex_gelas.S \ 213 lib/cpus/aarch64/nevis.S \ 214 lib/cpus/aarch64/travis.S 215endif 216 217else 218FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 219 lib/cpus/aarch32/cortex_a57.S \ 220 lib/cpus/aarch32/cortex_a53.S 221endif 222 223BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 224 drivers/arm/sp805/sp805.c \ 225 drivers/delay_timer/delay_timer.c \ 226 drivers/io/io_semihosting.c \ 227 lib/semihosting/semihosting.c \ 228 lib/semihosting/${ARCH}/semihosting_call.S \ 229 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 230 plat/arm/board/fvp/fvp_bl1_setup.c \ 231 plat/arm/board/fvp/fvp_cpu_pwr.c \ 232 plat/arm/board/fvp/fvp_err.c \ 233 plat/arm/board/fvp/fvp_io_storage.c \ 234 plat/arm/board/fvp/fvp_topology.c \ 235 ${FVP_CPU_LIBS} \ 236 ${FVP_INTERCONNECT_SOURCES} 237 238ifeq (${USE_SP804_TIMER},1) 239BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 240else 241BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 242endif 243 244 245BL2_SOURCES += drivers/arm/sp805/sp805.c \ 246 drivers/io/io_semihosting.c \ 247 lib/utils/mem_region.c \ 248 lib/semihosting/semihosting.c \ 249 lib/semihosting/${ARCH}/semihosting_call.S \ 250 plat/arm/board/fvp/fvp_bl2_setup.c \ 251 plat/arm/board/fvp/fvp_err.c \ 252 plat/arm/board/fvp/fvp_io_storage.c \ 253 plat/arm/common/arm_nor_psci_mem_protect.c \ 254 ${FVP_SECURITY_SOURCES} 255 256 257ifeq (${COT_DESC_IN_DTB},1) 258BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 259endif 260 261ifeq (${ENABLE_RME},1) 262BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 263 plat/arm/board/fvp/fvp_cpu_pwr.c 264 265BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 266 plat/arm/board/fvp/fvp_realm_attest_key.c 267endif 268 269ifeq (${ENABLE_FEAT_RNG_TRAP},1) 270BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 271endif 272 273ifeq (${RESET_TO_BL2},1) 274BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 275 plat/arm/board/fvp/fvp_cpu_pwr.c \ 276 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 277 ${FVP_CPU_LIBS} \ 278 ${FVP_INTERCONNECT_SOURCES} 279endif 280 281ifeq (${USE_SP804_TIMER},1) 282BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 283endif 284 285BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 286 ${FVP_SECURITY_SOURCES} 287 288ifeq (${USE_SP804_TIMER},1) 289BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 290endif 291 292BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 293 drivers/arm/smmu/smmu_v3.c \ 294 drivers/delay_timer/delay_timer.c \ 295 drivers/cfi/v2m/v2m_flash.c \ 296 lib/utils/mem_region.c \ 297 plat/arm/board/fvp/fvp_bl31_setup.c \ 298 plat/arm/board/fvp/fvp_console.c \ 299 plat/arm/board/fvp/fvp_pm.c \ 300 plat/arm/board/fvp/fvp_topology.c \ 301 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 302 plat/arm/board/fvp/fvp_cpu_pwr.c \ 303 plat/arm/common/arm_nor_psci_mem_protect.c \ 304 ${FVP_CPU_LIBS} \ 305 ${FVP_GIC_SOURCES} \ 306 ${FVP_INTERCONNECT_SOURCES} \ 307 ${FVP_SECURITY_SOURCES} 308 309# Support for fconf in BL31 310# Added separately from the above list for better readability 311ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 312BL31_SOURCES += lib/fconf/fconf.c \ 313 lib/fconf/fconf_dyn_cfg_getter.c \ 314 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 315 316BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 317 318ifeq (${SEC_INT_DESC_IN_FCONF},1) 319BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 320endif 321 322endif 323 324ifeq (${USE_SP804_TIMER},1) 325BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 326else 327BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 328endif 329 330# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 331ifdef UNIX_MK 332FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 333FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 334 335FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 336$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 337 338ifeq (${TRANSFER_LIST}, 1) 339FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 340 ${PLAT}_tb_fw_config.dts \ 341 ) 342else 343FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 344 ${PLAT}_fw_config.dts \ 345 ${PLAT}_tb_fw_config.dts \ 346 ${PLAT}_soc_fw_config.dts \ 347 ${PLAT}_nt_fw_config.dts \ 348 ) 349 350FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 351FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 352FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 353 354ifeq (${SPD},tspd) 355FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 356FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 357 358# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 359$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 360endif 361 362ifeq (${SPD},spmd) 363 364ifeq ($(ARM_SPMC_MANIFEST_DTS),) 365ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 366endif 367 368FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 369FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 370 371# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 373endif 374 375# Add the FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 377# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 379# Add the NT_FW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 381endif 382 383# Add the TB_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 385# Add the HW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 387endif 388 389ifeq (${TRANSFER_LIST}, 1) 390include lib/transfer_list/transfer_list.mk 391 392ifeq ($(RESET_TO_BL31), 1) 393HW_CONFIG := ${FVP_HW_CONFIG} 394FW_HANDOFF_SIZE := 20000 395 396$(eval $(call add_define,ARM_PRELOADED_DTB_OFFSET)) 397endif 398endif 399 400# Enable dynamic mitigation support by default 401DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 402 403ifneq (${ENABLE_FEAT_AMU},0) 404BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 405 lib/cpus/aarch64/cpuamu_helpers.S 406 407ifeq (${HW_ASSISTED_COHERENCY}, 1) 408BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 409 lib/cpus/aarch64/neoverse_n1_pubsub.c 410endif 411endif 412 413ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 414 ifeq (${ENABLE_FEAT_RAS},1) 415 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 416 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 417 else 418 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 419 endif 420 else 421 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 422 endif 423endif 424 425ifneq (${ENABLE_STACK_PROTECTOR},0) 426PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 427endif 428 429# Enable the dynamic translation tables library. 430ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 431 ifeq (${ARCH},aarch32) 432 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 433 else # AArch64 434 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 435 endif 436endif 437 438ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 439 ifeq (${ARCH},aarch32) 440 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 441 else # AArch64 442 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 443 ifeq (${SPD},tspd) 444 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 445 endif 446 endif 447endif 448 449ifeq (${USE_DEBUGFS},1) 450 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 451endif 452 453# Add support for platform supplied linker script for BL31 build 454$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 455 456ifneq (${RESET_TO_BL2}, 0) 457 override BL1_SOURCES = 458endif 459 460include plat/arm/board/common/board_common.mk 461include plat/arm/common/arm_common.mk 462 463ifeq (${MEASURED_BOOT},1) 464BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 465 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 466 lib/psa/measured_boot.c 467 468BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 469 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 470 lib/psa/measured_boot.c 471endif 472 473ifeq (${DRTM_SUPPORT}, 1) 474BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 475 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 476 plat/arm/board/fvp/fvp_drtm_err.c \ 477 plat/arm/board/fvp/fvp_drtm_measurement.c \ 478 plat/arm/board/fvp/fvp_drtm_stub.c \ 479 plat/arm/common/arm_dyn_cfg.c \ 480 plat/arm/board/fvp/fvp_err.c 481endif 482 483ifeq (${TRUSTED_BOARD_BOOT}, 1) 484BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 485BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 486 487# FVP being a development platform, enable capability to disable Authentication 488# dynamically if TRUSTED_BOARD_BOOT is set. 489DYN_DISABLE_AUTH := 1 490endif 491 492ifeq (${SPMC_AT_EL3}, 1) 493PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 494endif 495 496PSCI_OS_INIT_MODE := 1 497 498ifeq (${SPD},spmd) 499BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 500endif 501 502# Test specific macros, keep them at bottom of this file 503$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 504ifeq (${PLATFORM_TEST_EA_FFH}, 1) 505 ifeq (${FFH_SUPPORT}, 0) 506 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 507 endif 508 509endif 510 511$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 512ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 513 ifeq (${ENABLE_FEAT_RAS}, 0) 514 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 515 endif 516 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 517 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 518 endif 519endif 520 521$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 522ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 523 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 524 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 525 endif 526 ifeq (${ENABLE_SPMD_LP}, 0) 527 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 528 endif 529 ifeq (${ENABLE_FEAT_RAS}, 0) 530 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 531 endif 532 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 533 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 534 endif 535endif 536 537ifeq (${ERRATA_ABI_SUPPORT}, 1) 538include plat/arm/board/fvp/fvp_cpu_errata.mk 539endif 540 541# Build macro necessary for running SPM tests on FVP platform 542$(eval $(call add_define,PLAT_TEST_SPM)) 543