1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. This option defaults to 256. 34FVP_TRUSTED_SRAM_SIZE := 256 35 36# Macro to enable helpers for running SPM tests. Disabled by default. 37PLAT_TEST_SPM := 0 38 39# By default dont build CPUs with no FVP model. 40BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 41 42ENABLE_FEAT_AMU := 2 43ENABLE_FEAT_AMUv1p1 := 2 44ENABLE_FEAT_HCX := 2 45ENABLE_FEAT_RNG := 2 46ENABLE_FEAT_TWED := 2 47ENABLE_FEAT_GCS := 2 48 49ifeq (${ARCH}, aarch64) 50 51ifeq (${SPM_MM}, 0) 52ifeq (${CTX_INCLUDE_FPREGS}, 0) 53 ENABLE_SME_FOR_NS := 2 54 ENABLE_SME2_FOR_NS := 2 55else 56 ENABLE_SVE_FOR_NS := 0 57 ENABLE_SME_FOR_NS := 0 58 ENABLE_SME2_FOR_NS := 0 59endif 60endif 61 62 ENABLE_BRBE_FOR_NS := 2 63 ENABLE_TRBE_FOR_NS := 2 64 ENABLE_FEAT_D128 := 2 65 ENABLE_FEAT_FPMR := 2 66 ENABLE_FEAT_MOPS := 2 67endif 68 69ENABLE_SYS_REG_TRACE_FOR_NS := 2 70ENABLE_FEAT_CSV2_2 := 2 71ENABLE_FEAT_CSV2_3 := 2 72ENABLE_FEAT_DEBUGV8P9 := 2 73ENABLE_FEAT_DIT := 2 74ENABLE_FEAT_PAN := 2 75ENABLE_FEAT_VHE := 2 76CTX_INCLUDE_NEVE_REGS := 2 77ENABLE_FEAT_SEL2 := 2 78ENABLE_TRF_FOR_NS := 2 79ENABLE_FEAT_ECV := 2 80ENABLE_FEAT_FGT := 2 81ENABLE_FEAT_FGT2 := 2 82ENABLE_FEAT_THE := 2 83ENABLE_FEAT_TCR2 := 2 84ENABLE_FEAT_S2PIE := 2 85ENABLE_FEAT_S1PIE := 2 86ENABLE_FEAT_S2POE := 2 87ENABLE_FEAT_S1POE := 2 88ENABLE_FEAT_SCTLR2 := 2 89ENABLE_FEAT_MTE2 := 2 90ENABLE_FEAT_LS64_ACCDATA := 2 91 92# The FVP platform depends on this macro to build with correct GIC driver. 93$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 94 95# Pass FVP_CLUSTER_COUNT to the build system. 96$(eval $(call add_define,FVP_CLUSTER_COUNT)) 97 98# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 99$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 100 101# Pass FVP_MAX_PE_PER_CPU to the build system. 102$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 103 104# Pass FVP_GICR_REGION_PROTECTION to the build system. 105$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 106 107# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 108$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 109 110# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 111# choose the CCI driver , else the CCN driver 112ifeq ($(FVP_CLUSTER_COUNT), 0) 113$(error "Incorrect cluster count specified for FVP port") 114else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 115FVP_INTERCONNECT_DRIVER := FVP_CCI 116else 117FVP_INTERCONNECT_DRIVER := FVP_CCN 118endif 119 120$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 121 122# Choose the GIC sources depending upon the how the FVP will be invoked 123ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 124 125# The GIC model (GIC-600 or GIC-500) will be detected at runtime 126GICV3_SUPPORT_GIC600 := 1 127GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 128 129# Include GICv3 driver files 130include drivers/arm/gic/v3/gicv3.mk 131 132FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 133 plat/common/plat_gicv3.c \ 134 plat/arm/common/arm_gicv3.c 135 136 ifeq ($(filter 1,${RESET_TO_BL2} \ 137 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 138 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139 endif 140 141else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 142 143# No GICv4 extension 144GIC_ENABLE_V4_EXTN := 0 145$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 146 147# Include GICv2 driver files 148include drivers/arm/gic/v2/gicv2.mk 149 150FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 151 plat/common/plat_gicv2.c \ 152 plat/arm/common/arm_gicv2.c 153 154FVP_DT_PREFIX := fvp-base-gicv2-psci 155else 156$(error "Incorrect GIC driver chosen on FVP port") 157endif 158 159ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 160FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 161else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 162FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 163 plat/arm/common/arm_ccn.c 164else 165$(error "Incorrect CCN driver chosen on FVP port") 166endif 167 168FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 169 plat/arm/board/fvp/fvp_security.c \ 170 plat/arm/common/arm_tzc400.c 171 172 173PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 174 -Iinclude/lib/psa 175 176 177PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 178 179FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 180 181ifeq (${ARCH}, aarch64) 182 183# select a different set of CPU files, depending on whether we compile for 184# hardware assisted coherency cores or not 185ifeq (${HW_ASSISTED_COHERENCY}, 0) 186# Cores used without DSU 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 188 lib/cpus/aarch64/cortex_a53.S \ 189 lib/cpus/aarch64/cortex_a57.S \ 190 lib/cpus/aarch64/cortex_a72.S \ 191 lib/cpus/aarch64/cortex_a73.S 192else 193# Cores used with DSU only 194 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 195 # AArch64-only cores 196 # TODO: add all cores to the appropriate lists 197 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 198 lib/cpus/aarch64/cortex_a65ae.S \ 199 lib/cpus/aarch64/cortex_a76.S \ 200 lib/cpus/aarch64/cortex_a76ae.S \ 201 lib/cpus/aarch64/cortex_a77.S \ 202 lib/cpus/aarch64/cortex_a78.S \ 203 lib/cpus/aarch64/cortex_a78_ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_a710.S \ 206 lib/cpus/aarch64/cortex_a715.S \ 207 lib/cpus/aarch64/cortex_a720.S \ 208 lib/cpus/aarch64/cortex_a720_ae.S \ 209 lib/cpus/aarch64/neoverse_n_common.S \ 210 lib/cpus/aarch64/neoverse_n1.S \ 211 lib/cpus/aarch64/neoverse_n2.S \ 212 lib/cpus/aarch64/neoverse_v1.S \ 213 lib/cpus/aarch64/neoverse_e1.S \ 214 lib/cpus/aarch64/cortex_x2.S \ 215 lib/cpus/aarch64/cortex_x4.S 216 endif 217 # AArch64/AArch32 cores 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 219 lib/cpus/aarch64/cortex_a75.S 220endif 221 222#Include all CPUs to build to support all-errata build. 223ifeq (${ENABLE_ERRATA_ALL},1) 224 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 225 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ 226 lib/cpus/aarch64/cortex_a520.S \ 227 lib/cpus/aarch64/cortex_a725.S \ 228 lib/cpus/aarch64/cortex_x1.S \ 229 lib/cpus/aarch64/cortex_x3.S \ 230 lib/cpus/aarch64/cortex_x925.S \ 231 lib/cpus/aarch64/neoverse_n3.S \ 232 lib/cpus/aarch64/neoverse_v2.S \ 233 lib/cpus/aarch64/neoverse_v3.S 234endif 235 236#Build AArch64-only CPUs with no FVP model yet. 237ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 238 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 239 lib/cpus/aarch64/cortex_gelas.S \ 240 lib/cpus/aarch64/nevis.S \ 241 lib/cpus/aarch64/travis.S \ 242 lib/cpus/aarch64/cortex_arcadia.S \ 243 lib/cpus/aarch64/cortex_alto.S 244endif 245 246else 247FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 248 lib/cpus/aarch32/cortex_a57.S \ 249 lib/cpus/aarch32/cortex_a53.S 250endif 251 252BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 253 drivers/arm/sp805/sp805.c \ 254 drivers/delay_timer/delay_timer.c \ 255 drivers/io/io_semihosting.c \ 256 lib/semihosting/semihosting.c \ 257 lib/semihosting/${ARCH}/semihosting_call.S \ 258 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 259 plat/arm/board/fvp/fvp_bl1_setup.c \ 260 plat/arm/board/fvp/fvp_cpu_pwr.c \ 261 plat/arm/board/fvp/fvp_err.c \ 262 plat/arm/board/fvp/fvp_io_storage.c \ 263 plat/arm/board/fvp/fvp_topology.c \ 264 ${FVP_CPU_LIBS} \ 265 ${FVP_INTERCONNECT_SOURCES} 266 267ifeq (${USE_SP804_TIMER},1) 268BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 269else 270BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 271endif 272 273 274BL2_SOURCES += drivers/arm/sp805/sp805.c \ 275 drivers/io/io_semihosting.c \ 276 lib/utils/mem_region.c \ 277 lib/semihosting/semihosting.c \ 278 lib/semihosting/${ARCH}/semihosting_call.S \ 279 plat/arm/board/fvp/fvp_bl2_setup.c \ 280 plat/arm/board/fvp/fvp_err.c \ 281 plat/arm/board/fvp/fvp_io_storage.c \ 282 plat/arm/common/arm_nor_psci_mem_protect.c \ 283 ${FVP_SECURITY_SOURCES} 284 285 286ifeq (${COT_DESC_IN_DTB},1) 287BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 288endif 289 290ifeq (${ENABLE_RME},1) 291BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 292 plat/arm/board/fvp/fvp_cpu_pwr.c 293 294BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 295 plat/arm/board/fvp/fvp_realm_attest_key.c \ 296 plat/arm/board/fvp/fvp_el3_token_sign.c 297endif 298 299ifeq (${ENABLE_FEAT_RNG_TRAP},1) 300BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 301endif 302 303ifeq (${RESET_TO_BL2},1) 304BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 305 plat/arm/board/fvp/fvp_cpu_pwr.c \ 306 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 307 ${FVP_CPU_LIBS} \ 308 ${FVP_INTERCONNECT_SOURCES} 309endif 310 311ifeq (${USE_SP804_TIMER},1) 312BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 313endif 314 315BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 316 ${FVP_SECURITY_SOURCES} 317 318ifeq (${USE_SP804_TIMER},1) 319BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 320endif 321 322BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 323 drivers/arm/smmu/smmu_v3.c \ 324 drivers/delay_timer/delay_timer.c \ 325 drivers/cfi/v2m/v2m_flash.c \ 326 lib/utils/mem_region.c \ 327 plat/arm/board/fvp/fvp_bl31_setup.c \ 328 plat/arm/board/fvp/fvp_console.c \ 329 plat/arm/board/fvp/fvp_pm.c \ 330 plat/arm/board/fvp/fvp_topology.c \ 331 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 332 plat/arm/board/fvp/fvp_cpu_pwr.c \ 333 plat/arm/common/arm_nor_psci_mem_protect.c \ 334 ${FVP_CPU_LIBS} \ 335 ${FVP_GIC_SOURCES} \ 336 ${FVP_INTERCONNECT_SOURCES} \ 337 ${FVP_SECURITY_SOURCES} 338 339# Support for fconf in BL31 340# Added separately from the above list for better readability 341ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 342BL31_SOURCES += lib/fconf/fconf.c \ 343 lib/fconf/fconf_dyn_cfg_getter.c \ 344 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 345 346BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 347 348ifeq (${SEC_INT_DESC_IN_FCONF},1) 349BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 350endif 351 352endif 353 354ifeq (${USE_SP804_TIMER},1) 355BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 356else 357BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 358endif 359 360# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 361FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 362 363FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 364$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 365 366ifeq (${TRANSFER_LIST}, 0) 367FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 368 ${PLAT}_fw_config.dts \ 369 ${PLAT}_tb_fw_config.dts \ 370 ${PLAT}_soc_fw_config.dts \ 371 ${PLAT}_nt_fw_config.dts \ 372 ) 373 374FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 375FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 376FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 377FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 378 379ifeq (${SPD},tspd) 380FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 381FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 382 383# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 385endif 386 387ifeq (${SPD},spmd) 388 389ifeq ($(ARM_SPMC_MANIFEST_DTS),) 390ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 391endif 392 393FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 394FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 395 396# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 397$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 398endif 399 400# Add the FW_CONFIG to FIP and specify the same to certtool 401$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 402# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 403$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 404# Add the NT_FW_CONFIG to FIP and specify the same to certtool 405$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 406# Add the TB_FW_CONFIG to FIP and specify the same to certtool 407$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 408endif 409 410# Add the HW_CONFIG to FIP and specify the same to certtool 411$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 412 413ifeq (${TRANSFER_LIST}, 1) 414include lib/transfer_list/transfer_list.mk 415 416ifeq ($(RESET_TO_BL31), 1) 417HW_CONFIG := ${FVP_HW_CONFIG} 418FW_HANDOFF_SIZE := 20000 419 420TRANSFER_LIST_DTB_OFFSET := 0x20 421$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 422endif 423endif 424 425ifeq (${HOB_LIST}, 1) 426include lib/hob/hob.mk 427endif 428 429# Enable dynamic mitigation support by default 430DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 431 432ifneq (${ENABLE_FEAT_AMU},0) 433BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 434 lib/cpus/aarch64/cpuamu_helpers.S 435 436ifeq (${HW_ASSISTED_COHERENCY}, 1) 437BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 438 lib/cpus/aarch64/neoverse_n1_pubsub.c 439endif 440endif 441 442ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 443 ifeq (${ENABLE_FEAT_RAS},1) 444 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 445 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 446 else 447 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 448 endif 449 else 450 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 451 endif 452endif 453 454ifneq (${ENABLE_STACK_PROTECTOR},0) 455PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 456endif 457 458# Enable the dynamic translation tables library. 459ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 460 ifeq (${ARCH},aarch32) 461 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 462 else # AArch64 463 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 464 endif 465endif 466 467ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 468 ifeq (${ARCH},aarch32) 469 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 470 else # AArch64 471 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 472 ifeq (${SPD},tspd) 473 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 474 endif 475 endif 476endif 477 478ifeq (${USE_DEBUGFS},1) 479 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 480endif 481 482# Add support for platform supplied linker script for BL31 build 483$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 484 485ifneq (${RESET_TO_BL2}, 0) 486 override BL1_SOURCES = 487endif 488 489include plat/arm/board/common/board_common.mk 490include plat/arm/common/arm_common.mk 491 492ifeq (${MEASURED_BOOT},1) 493BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 494 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 495 lib/psa/measured_boot.c 496 497BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 498 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 499 lib/psa/measured_boot.c 500endif 501 502ifeq (${DRTM_SUPPORT}, 1) 503BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 504 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 505 plat/arm/board/fvp/fvp_drtm_err.c \ 506 plat/arm/board/fvp/fvp_drtm_measurement.c \ 507 plat/arm/board/fvp/fvp_drtm_stub.c \ 508 plat/arm/common/arm_dyn_cfg.c \ 509 plat/arm/board/fvp/fvp_err.c 510endif 511 512ifeq (${TRUSTED_BOARD_BOOT}, 1) 513BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 514BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 515 516# FVP being a development platform, enable capability to disable Authentication 517# dynamically if TRUSTED_BOARD_BOOT is set. 518DYN_DISABLE_AUTH := 1 519endif 520 521ifeq (${SPMC_AT_EL3}, 1) 522PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 523endif 524 525PSCI_OS_INIT_MODE := 1 526 527ifeq (${SPD},spmd) 528BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 529endif 530 531# Test specific macros, keep them at bottom of this file 532$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 533ifeq (${PLATFORM_TEST_EA_FFH}, 1) 534 ifeq (${FFH_SUPPORT}, 0) 535 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 536 endif 537 538endif 539 540$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 541ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 542 ifeq (${ENABLE_FEAT_RAS}, 0) 543 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 544 endif 545 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 546 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 547 endif 548endif 549 550$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 551ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 552 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 553 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 554 endif 555 ifeq (${ENABLE_SPMD_LP}, 0) 556 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 557 endif 558 ifeq (${ENABLE_FEAT_RAS}, 0) 559 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 560 endif 561 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 562 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 563 endif 564endif 565 566ifeq (${ERRATA_ABI_SUPPORT}, 1) 567include plat/arm/board/fvp/fvp_cpu_errata.mk 568endif 569 570# Build macro necessary for running SPM tests on FVP platform 571$(eval $(call add_define,PLAT_TEST_SPM)) 572