1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39ENABLE_FEAT_AMU := 2 40ENABLE_FEAT_AMUv1p1 := 2 41ENABLE_FEAT_HCX := 2 42ENABLE_FEAT_RNG := 2 43ENABLE_FEAT_TWED := 2 44ENABLE_FEAT_GCS := 2 45 46ifeq (${ARCH}, aarch64) 47 48ifeq (${SPM_MM}, 0) 49ifeq (${CTX_INCLUDE_FPREGS}, 0) 50 ENABLE_SME_FOR_NS := 2 51 ENABLE_SME2_FOR_NS := 2 52else 53 ENABLE_SVE_FOR_NS := 0 54 ENABLE_SME_FOR_NS := 0 55 ENABLE_SME2_FOR_NS := 0 56endif 57endif 58 59 ENABLE_BRBE_FOR_NS := 2 60 ENABLE_TRBE_FOR_NS := 2 61 ENABLE_FEAT_D128 := 2 62 ENABLE_FEAT_FPMR := 2 63 ENABLE_FEAT_MOPS := 2 64 ENABLE_FEAT_FGWTE3 := 2 65 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 66 ENABLE_FEAT_CPA2 := 2 67 ENABLE_FEAT_UINJ := 2 68endif 69 70ENABLE_SYS_REG_TRACE_FOR_NS := 2 71ENABLE_FEAT_CSV2_2 := 2 72ENABLE_FEAT_CSV2_3 := 2 73ENABLE_FEAT_CLRBHB := 2 74ENABLE_FEAT_DEBUGV8P9 := 2 75ENABLE_FEAT_DIT := 2 76ENABLE_FEAT_PAN := 2 77ENABLE_FEAT_VHE := 2 78CTX_INCLUDE_NEVE_REGS := 2 79ENABLE_FEAT_SEL2 := 2 80ENABLE_TRF_FOR_NS := 2 81ENABLE_FEAT_ECV := 2 82ENABLE_FEAT_FGT := 2 83ENABLE_FEAT_FGT2 := 2 84ENABLE_FEAT_THE := 2 85ENABLE_FEAT_TCR2 := 2 86ENABLE_FEAT_S2PIE := 2 87ENABLE_FEAT_S1PIE := 2 88ENABLE_FEAT_S2POE := 2 89ENABLE_FEAT_S1POE := 2 90ENABLE_FEAT_SCTLR2 := 2 91ENABLE_FEAT_MTE2 := 2 92ENABLE_FEAT_LS64_ACCDATA := 2 93ENABLE_FEAT_AIE := 2 94ENABLE_FEAT_PFAR := 2 95ENABLE_FEAT_EBEP := 2 96 97ifeq (${ENABLE_RME},1) 98 ENABLE_FEAT_MEC := 2 99 RMMD_ENABLE_IDE_KEY_PROG := 1 100endif 101 102# The FVP platform depends on this macro to build with correct GIC driver. 103$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 104 105# Pass FVP_CLUSTER_COUNT to the build system. 106$(eval $(call add_define,FVP_CLUSTER_COUNT)) 107 108# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 109$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 110 111# Pass FVP_MAX_PE_PER_CPU to the build system. 112$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 113 114# Pass FVP_GICR_REGION_PROTECTION to the build system. 115$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 116 117# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 118$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 119 120ifeq (${DRTM_SUPPORT},1) 121MBOOT_EL_HASH_ALG := sha256 122endif 123 124# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 125# choose the CCI driver , else the CCN driver 126ifeq ($(FVP_CLUSTER_COUNT), 0) 127$(error "Incorrect cluster count specified for FVP port") 128else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 129FVP_INTERCONNECT_DRIVER := FVP_CCI 130else 131FVP_INTERCONNECT_DRIVER := FVP_CCN 132endif 133 134$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 135 136# Choose the GIC sources depending upon the how the FVP will be invoked 137ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 138USE_GIC_DRIVER := 3 139 140# The GIC model (GIC-600 or GIC-500) will be detected at runtime 141GICV3_SUPPORT_GIC600 := 1 142GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 143 144FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 145ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 146BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 147endif 148 149ifeq (${HW_ASSISTED_COHERENCY}, 0) 150FVP_DT_PREFIX := fvp-base-gicv3-psci 151else 152FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 153endif 154else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 155USE_GIC_DRIVER := 5 156ENABLE_FEAT_GCIE := 1 157BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 158FVP_DT_PREFIX := fvp-base-gicv5-psci 159ifneq ($(SPD),none) 160 $(error Error: GICv5 is not compatible with SPDs) 161endif 162ifeq ($(ENABLE_RME),1) 163 $(error Error: GICv5 is not compatible with RME) 164endif 165else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 166USE_GIC_DRIVER := 2 167 168# No GICv4 extension 169GIC_ENABLE_V4_EXTN := 0 170$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 171 172FVP_DT_PREFIX := fvp-base-gicv2-psci 173else 174$(error "Incorrect GIC driver chosen on FVP port") 175endif 176 177ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 178FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 179else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 180FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 181 plat/arm/common/arm_ccn.c 182else 183$(error "Incorrect CCN driver chosen on FVP port") 184endif 185 186FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 187 plat/arm/board/fvp/fvp_security.c \ 188 plat/arm/common/arm_tzc400.c 189 190 191PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 192 -Iinclude/lib/psa 193 194 195PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 196 197FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 198 199ifeq (${ARCH}, aarch64) 200 201# select a different set of CPU files, depending on whether we compile for 202# hardware assisted coherency cores or not 203ifeq (${HW_ASSISTED_COHERENCY}, 0) 204# Cores used without DSU 205 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 206 lib/cpus/aarch64/cortex_a53.S \ 207 lib/cpus/aarch64/cortex_a57.S \ 208 lib/cpus/aarch64/cortex_a72.S \ 209 lib/cpus/aarch64/cortex_a73.S 210else 211# Cores used with DSU only 212 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 213 # AArch64-only cores 214 # TODO: add all cores to the appropriate lists 215 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 216 lib/cpus/aarch64/cortex_a65ae.S \ 217 lib/cpus/aarch64/cortex_a76.S \ 218 lib/cpus/aarch64/cortex_a76ae.S \ 219 lib/cpus/aarch64/cortex_a77.S \ 220 lib/cpus/aarch64/cortex_a78.S \ 221 lib/cpus/aarch64/cortex_a78_ae.S \ 222 lib/cpus/aarch64/cortex_a78c.S \ 223 lib/cpus/aarch64/cortex_a710.S \ 224 lib/cpus/aarch64/cortex_a715.S \ 225 lib/cpus/aarch64/cortex_a720.S \ 226 lib/cpus/aarch64/cortex_a720_ae.S \ 227 lib/cpus/aarch64/neoverse_n1.S \ 228 lib/cpus/aarch64/neoverse_n2.S \ 229 lib/cpus/aarch64/neoverse_v1.S \ 230 lib/cpus/aarch64/neoverse_e1.S \ 231 lib/cpus/aarch64/cortex_x2.S \ 232 lib/cpus/aarch64/cortex_x4.S 233 endif 234 # AArch64/AArch32 cores 235 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 236 lib/cpus/aarch64/cortex_a75.S 237endif 238 239#Include all CPUs to build to support all-errata build. 240ifeq (${ENABLE_ERRATA_ALL},1) 241 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 242 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 243 lib/cpus/aarch64/cortex_a510.S \ 244 lib/cpus/aarch64/cortex_a520.S \ 245 lib/cpus/aarch64/cortex_a725.S \ 246 lib/cpus/aarch64/cortex_x1.S \ 247 lib/cpus/aarch64/cortex_x3.S \ 248 lib/cpus/aarch64/cortex_x925.S \ 249 lib/cpus/aarch64/neoverse_n3.S \ 250 lib/cpus/aarch64/neoverse_v2.S \ 251 lib/cpus/aarch64/neoverse_v3.S 252endif 253 254#Build AArch64-only CPUs with no FVP model yet. 255ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 256 ERRATA_SME_POWER_DOWN := 1 257 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 258 lib/cpus/aarch64/c1_nano.S \ 259 lib/cpus/aarch64/c1_ultra.S \ 260 lib/cpus/aarch64/c1_premium.S \ 261 lib/cpus/aarch64/canyon.S \ 262 lib/cpus/aarch64/caddo.S \ 263 lib/cpus/aarch64/veymont.S \ 264 lib/cpus/aarch64/dionysus.S \ 265 lib/cpus/aarch64/venom.S \ 266 lib/cpus/aarch64/lsc25_p_core.S \ 267 lib/cpus/aarch64/lsc25_e_core.S 268endif 269 270else 271FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 272 lib/cpus/aarch32/cortex_a57.S \ 273 lib/cpus/aarch32/cortex_a53.S 274endif 275 276BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 277 drivers/arm/sp805/sp805.c \ 278 drivers/delay_timer/delay_timer.c \ 279 drivers/io/io_semihosting.c \ 280 lib/semihosting/semihosting.c \ 281 lib/semihosting/${ARCH}/semihosting_call.S \ 282 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 283 plat/arm/board/fvp/fvp_bl1_setup.c \ 284 plat/arm/board/fvp/fvp_cpu_pwr.c \ 285 plat/arm/board/fvp/fvp_err.c \ 286 plat/arm/board/fvp/fvp_io_storage.c \ 287 plat/arm/board/fvp/fvp_topology.c \ 288 ${FVP_CPU_LIBS} \ 289 ${FVP_INTERCONNECT_SOURCES} 290 291ifeq (${USE_SP804_TIMER},1) 292BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 293else 294BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 295endif 296 297 298BL2_SOURCES += drivers/arm/sp805/sp805.c \ 299 drivers/io/io_semihosting.c \ 300 lib/utils/mem_region.c \ 301 lib/semihosting/semihosting.c \ 302 lib/semihosting/${ARCH}/semihosting_call.S \ 303 plat/arm/board/fvp/fvp_bl2_setup.c \ 304 plat/arm/board/fvp/fvp_err.c \ 305 plat/arm/board/fvp/fvp_io_storage.c \ 306 plat/arm/common/arm_nor_psci_mem_protect.c \ 307 ${FVP_SECURITY_SOURCES} 308 309 310ifeq (${COT_DESC_IN_DTB},1) 311BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 312endif 313 314ifeq (${ENABLE_RME},1) 315BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 316 plat/arm/board/fvp/fvp_cpu_pwr.c 317 318BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 319 plat/arm/board/fvp/fvp_realm_attest_key.c \ 320 plat/arm/board/fvp/fvp_el3_token_sign.c \ 321 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 322 plat/arm/common/plat_rmm_mem_carveout.c 323endif 324 325ifneq (${ENABLE_FEAT_RNG_TRAP},0) 326BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 327endif 328 329ifeq (${RESET_TO_BL2},1) 330BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 331 plat/arm/board/fvp/fvp_cpu_pwr.c \ 332 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 333 ${FVP_CPU_LIBS} \ 334 ${FVP_INTERCONNECT_SOURCES} 335endif 336 337ifeq (${USE_SP804_TIMER},1) 338BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 339endif 340 341BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 342 ${FVP_SECURITY_SOURCES} 343 344ifeq (${USE_SP804_TIMER},1) 345BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 346endif 347 348BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 349 drivers/arm/smmu/smmu_v3.c \ 350 drivers/delay_timer/delay_timer.c \ 351 drivers/cfi/v2m/v2m_flash.c \ 352 lib/utils/mem_region.c \ 353 plat/arm/board/fvp/fvp_bl31_setup.c \ 354 plat/arm/board/fvp/fvp_console.c \ 355 plat/arm/board/fvp/fvp_pm.c \ 356 plat/arm/board/fvp/fvp_topology.c \ 357 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 358 plat/arm/board/fvp/fvp_cpu_pwr.c \ 359 plat/arm/common/arm_nor_psci_mem_protect.c \ 360 ${FVP_CPU_LIBS} \ 361 ${FVP_INTERCONNECT_SOURCES} \ 362 ${FVP_SECURITY_SOURCES} 363 364# Support for fconf in BL31 365# Added separately from the above list for better readability 366ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 367BL31_SOURCES += lib/fconf/fconf.c \ 368 lib/fconf/fconf_dyn_cfg_getter.c \ 369 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 370 371BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 372 373ifeq (${SEC_INT_DESC_IN_FCONF},1) 374BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 375endif 376 377endif 378 379ifeq (${USE_SP804_TIMER},1) 380BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 381else 382BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 383endif 384 385# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 386FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 387 388FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 389$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 390HW_CONFIG := ${FVP_HW_CONFIG} 391 392HW_CONFIG_BASE ?= 0x82000000 393 394# Set default initrd base 128MiB offset of the default kernel address in FVP 395INITRD_BASE ?= 0x90000000 396 397# Kernel base address supports Linux kernels before v5.7 398# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 399ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 400 PRELOADED_BL33_BASE ?= 0x80080000 401 ifeq (${RESET_TO_BL31},1) 402 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 403 endif 404endif 405 406ifeq (${TRANSFER_LIST}, 0) 407FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 408 ${PLAT}_fw_config.dts \ 409 ${PLAT}_tb_fw_config.dts \ 410 ${PLAT}_soc_fw_config.dts \ 411 ${PLAT}_nt_fw_config.dts \ 412 ) 413 414FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 415FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 416FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 417FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 418 419ifeq (${SPD},tspd) 420FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 421FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 422 423# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 424$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 425endif 426 427# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 428$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 429# Add the NT_FW_CONFIG to FIP and specify the same to certtool 430$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 431endif 432 433ifeq (${SPD},spmd) 434 435ifeq ($(ARM_SPMC_MANIFEST_DTS),) 436ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 437endif 438 439FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 440FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 441 442# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 443$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 444endif 445 446# Add the HW_CONFIG to FIP and specify the same to certtool 447$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 448 449ifeq (${TRANSFER_LIST}, 1) 450 451ifeq ($(RESET_TO_BL31), 1) 452FW_HANDOFF_SIZE := 20000 453 454TRANSFER_LIST_DTB_OFFSET := 0x20 455$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 456endif 457 458# 459# To load SP_PKGs with TRANSFER_LIST, FVP_TB_FW_CONFIG is required. 460# 461ifeq (${BL2_ENABLE_SP_LOAD}, 1) 462 FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 463 ${PLAT}_tb_fw_config.dts \ 464 ) 465 466 FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 467 468 # Add the TB_FW_CONFIG to FIP and specify the same to certtool 469 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 470endif 471 472endif 473 474ifeq (${HOB_LIST}, 1) 475include lib/hob/hob.mk 476endif 477 478# Enable dynamic mitigation support by default 479DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 480 481ifneq (${ENABLE_FEAT_AMU},0) 482BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 483 lib/cpus/aarch64/cpuamu_helpers.S 484 485ifeq (${HW_ASSISTED_COHERENCY}, 1) 486BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 487 lib/cpus/aarch64/neoverse_n1_pubsub.c 488endif 489endif 490 491ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 492 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 493 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 494 endif 495 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 496 plat/arm/board/fvp/aarch64/fvp_ea.c 497endif 498 499ifneq (${ENABLE_STACK_PROTECTOR},0) 500PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 501endif 502 503# Enable the dynamic translation tables library. 504ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 505 ifeq (${ARCH},aarch32) 506 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 507 else # AArch64 508 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 509 endif 510endif 511 512ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 513 ifeq (${ARCH},aarch32) 514 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 515 else # AArch64 516 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 517 ifeq (${SPD},tspd) 518 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 519 endif 520 endif 521endif 522 523ifeq (${USE_DEBUGFS},1) 524 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 525endif 526 527# Add support for platform supplied linker script for BL31 build 528PLAT_EXTRA_LD_SCRIPT := 1 529 530ifneq (${RESET_TO_BL2}, 0) 531 override BL1_SOURCES = 532endif 533 534include plat/arm/board/common/board_common.mk 535include plat/arm/common/arm_common.mk 536 537ifeq (${MEASURED_BOOT},1) 538BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 539 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 540 lib/psa/measured_boot.c \ 541 common/measured_boot_helpers.c 542 543BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 544 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 545 lib/psa/measured_boot.c \ 546 common/measured_boot_helpers.c 547endif 548 549ifeq (${DRTM_SUPPORT}, 1) 550BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 551 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 552 plat/arm/board/fvp/fvp_drtm_err.c \ 553 plat/arm/board/fvp/fvp_drtm_measurement.c \ 554 plat/arm/board/fvp/fvp_drtm_stub.c \ 555 plat/arm/common/arm_dyn_cfg.c \ 556 plat/arm/board/fvp/fvp_err.c 557endif 558 559ifeq (${TRUSTED_BOARD_BOOT}, 1) 560BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 561BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 562 563# FVP being a development platform, enable capability to disable Authentication 564# dynamically if TRUSTED_BOARD_BOOT is set. 565DYN_DISABLE_AUTH := 1 566endif 567 568ifeq (${SPMC_AT_EL3}, 1) 569PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 570endif 571 572PSCI_OS_INIT_MODE := 1 573 574ifeq (${SPD},spmd) 575BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 576endif 577 578# Test specific macros, keep them at bottom of this file 579$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 580ifeq (${PLATFORM_TEST_EA_FFH}, 1) 581 ifeq (${FFH_SUPPORT}, 0) 582 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 583 endif 584 585endif 586 587PLATFORM_TEST_RAS_FFH ?= 0 588$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 589ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 590 ifeq (${ENABLE_FEAT_RAS}, 0) 591 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 592 endif 593 ifeq (${SDEI_SUPPORT}, 0) 594 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 595 endif 596 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 597 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 598 endif 599endif 600 601$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 602ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 603 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 604 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 605 endif 606 ifeq (${ENABLE_SPMD_LP}, 0) 607 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 608 endif 609 ifeq (${ENABLE_FEAT_RAS}, 0) 610 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 611 endif 612 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 613 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 614 endif 615endif 616 617ifeq (${ERRATA_ABI_SUPPORT}, 1) 618include plat/arm/board/fvp/fvp_cpu_errata.mk 619endif 620 621# Build macro necessary for running SPM tests on FVP platform 622$(eval $(call add_define,PLAT_TEST_SPM)) 623 624ifeq (${LFA_SUPPORT},1) 625BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 626endif 627 628# This is set to 1 by default when the firmware update 629# support is enabled. Since the BL2 image is not updatable 630ifeq ($(PSA_FWU_SUPPORT),1) 631 SEPARATE_BL2_FIP := 1 632endif 633 634ifeq (${TRANSFER_LIST}, 0) 635ifeq (${SEPARATE_BL2_FIP},1) 636$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 637$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 638else 639$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 640$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 641endif 642endif 643