1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39ENABLE_FEAT_AMU := 2 40ENABLE_FEAT_AMUv1p1 := 2 41ENABLE_FEAT_HCX := 2 42ENABLE_FEAT_RNG := 2 43ENABLE_FEAT_TWED := 2 44ENABLE_FEAT_GCS := 2 45 46ifeq (${ARCH}, aarch64) 47 48ifeq (${SPM_MM}, 0) 49ifeq (${CTX_INCLUDE_FPREGS}, 0) 50 ENABLE_SME_FOR_NS := 2 51 ENABLE_SME2_FOR_NS := 2 52else 53 ENABLE_SVE_FOR_NS := 0 54 ENABLE_SME_FOR_NS := 0 55 ENABLE_SME2_FOR_NS := 0 56endif 57endif 58 59 ENABLE_BRBE_FOR_NS := 2 60 ENABLE_TRBE_FOR_NS := 2 61 ENABLE_FEAT_D128 := 2 62 ENABLE_FEAT_FPMR := 2 63 ENABLE_FEAT_MOPS := 2 64 ENABLE_FEAT_FGWTE3 := 2 65 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 66 ENABLE_FEAT_CPA2 := 2 67endif 68 69ENABLE_SYS_REG_TRACE_FOR_NS := 2 70ENABLE_FEAT_CSV2_2 := 2 71ENABLE_FEAT_CSV2_3 := 2 72ENABLE_FEAT_CLRBHB := 2 73ENABLE_FEAT_DEBUGV8P9 := 2 74ENABLE_FEAT_DIT := 2 75ENABLE_FEAT_PAN := 2 76ENABLE_FEAT_VHE := 2 77CTX_INCLUDE_NEVE_REGS := 2 78ENABLE_FEAT_SEL2 := 2 79ENABLE_TRF_FOR_NS := 2 80ENABLE_FEAT_ECV := 2 81ENABLE_FEAT_FGT := 2 82ENABLE_FEAT_FGT2 := 2 83ENABLE_FEAT_THE := 2 84ENABLE_FEAT_TCR2 := 2 85ENABLE_FEAT_S2PIE := 2 86ENABLE_FEAT_S1PIE := 2 87ENABLE_FEAT_S2POE := 2 88ENABLE_FEAT_S1POE := 2 89ENABLE_FEAT_SCTLR2 := 2 90ENABLE_FEAT_MTE2 := 2 91ENABLE_FEAT_LS64_ACCDATA := 2 92ENABLE_FEAT_AIE := 2 93ENABLE_FEAT_PFAR := 2 94ENABLE_FEAT_EBEP := 2 95 96ifeq (${ENABLE_RME},1) 97 ENABLE_FEAT_MEC := 2 98 RMMD_ENABLE_IDE_KEY_PROG := 1 99endif 100 101# The FVP platform depends on this macro to build with correct GIC driver. 102$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 103 104# Pass FVP_CLUSTER_COUNT to the build system. 105$(eval $(call add_define,FVP_CLUSTER_COUNT)) 106 107# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 108$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 109 110# Pass FVP_MAX_PE_PER_CPU to the build system. 111$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 112 113# Pass FVP_GICR_REGION_PROTECTION to the build system. 114$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 115 116# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 117$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 118 119# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 120# choose the CCI driver , else the CCN driver 121ifeq ($(FVP_CLUSTER_COUNT), 0) 122$(error "Incorrect cluster count specified for FVP port") 123else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 124FVP_INTERCONNECT_DRIVER := FVP_CCI 125else 126FVP_INTERCONNECT_DRIVER := FVP_CCN 127endif 128 129$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 130 131# Choose the GIC sources depending upon the how the FVP will be invoked 132ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 133USE_GIC_DRIVER := 3 134 135# The GIC model (GIC-600 or GIC-500) will be detected at runtime 136GICV3_SUPPORT_GIC600 := 1 137GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 138 139FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 140ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 141BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 142endif 143 144ifeq (${HW_ASSISTED_COHERENCY}, 0) 145FVP_DT_PREFIX := fvp-base-gicv3-psci 146else 147FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 148endif 149else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 150USE_GIC_DRIVER := 5 151ENABLE_FEAT_GCIE := 1 152BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 153FVP_DT_PREFIX := fvp-base-gicv5-psci 154ifneq ($(SPD),none) 155 $(error Error: GICv5 is not compatible with SPDs) 156endif 157ifeq ($(ENABLE_RME),1) 158 $(error Error: GICv5 is not compatible with RME) 159endif 160else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 161USE_GIC_DRIVER := 2 162 163# No GICv4 extension 164GIC_ENABLE_V4_EXTN := 0 165$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 166 167FVP_DT_PREFIX := fvp-base-gicv2-psci 168else 169$(error "Incorrect GIC driver chosen on FVP port") 170endif 171 172ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 173FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 174else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 175FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 176 plat/arm/common/arm_ccn.c 177else 178$(error "Incorrect CCN driver chosen on FVP port") 179endif 180 181FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 182 plat/arm/board/fvp/fvp_security.c \ 183 plat/arm/common/arm_tzc400.c 184 185 186PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 187 -Iinclude/lib/psa 188 189 190PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 191 192FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 193 194ifeq (${ARCH}, aarch64) 195 196# select a different set of CPU files, depending on whether we compile for 197# hardware assisted coherency cores or not 198ifeq (${HW_ASSISTED_COHERENCY}, 0) 199# Cores used without DSU 200 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 201 lib/cpus/aarch64/cortex_a53.S \ 202 lib/cpus/aarch64/cortex_a57.S \ 203 lib/cpus/aarch64/cortex_a72.S \ 204 lib/cpus/aarch64/cortex_a73.S 205else 206# Cores used with DSU only 207 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 208 # AArch64-only cores 209 # TODO: add all cores to the appropriate lists 210 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 211 lib/cpus/aarch64/cortex_a65ae.S \ 212 lib/cpus/aarch64/cortex_a76.S \ 213 lib/cpus/aarch64/cortex_a76ae.S \ 214 lib/cpus/aarch64/cortex_a77.S \ 215 lib/cpus/aarch64/cortex_a78.S \ 216 lib/cpus/aarch64/cortex_a78_ae.S \ 217 lib/cpus/aarch64/cortex_a78c.S \ 218 lib/cpus/aarch64/cortex_a710.S \ 219 lib/cpus/aarch64/cortex_a715.S \ 220 lib/cpus/aarch64/cortex_a720.S \ 221 lib/cpus/aarch64/cortex_a720_ae.S \ 222 lib/cpus/aarch64/neoverse_n1.S \ 223 lib/cpus/aarch64/neoverse_n2.S \ 224 lib/cpus/aarch64/neoverse_v1.S \ 225 lib/cpus/aarch64/neoverse_e1.S \ 226 lib/cpus/aarch64/cortex_x2.S \ 227 lib/cpus/aarch64/cortex_x4.S 228 endif 229 # AArch64/AArch32 cores 230 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 231 lib/cpus/aarch64/cortex_a75.S 232endif 233 234#Include all CPUs to build to support all-errata build. 235ifeq (${ENABLE_ERRATA_ALL},1) 236 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 237 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 238 lib/cpus/aarch64/cortex_a510.S \ 239 lib/cpus/aarch64/cortex_a520.S \ 240 lib/cpus/aarch64/cortex_a725.S \ 241 lib/cpus/aarch64/cortex_x1.S \ 242 lib/cpus/aarch64/cortex_x3.S \ 243 lib/cpus/aarch64/cortex_x925.S \ 244 lib/cpus/aarch64/neoverse_n3.S \ 245 lib/cpus/aarch64/neoverse_v2.S \ 246 lib/cpus/aarch64/neoverse_v3.S 247endif 248 249#Build AArch64-only CPUs with no FVP model yet. 250ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 251 ERRATA_SME_POWER_DOWN := 1 252 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 253 lib/cpus/aarch64/c1_nano.S \ 254 lib/cpus/aarch64/c1_ultra.S \ 255 lib/cpus/aarch64/c1_premium.S \ 256 lib/cpus/aarch64/canyon.S \ 257 lib/cpus/aarch64/caddo.S \ 258 lib/cpus/aarch64/veymont.S \ 259 lib/cpus/aarch64/dionysus.S \ 260 lib/cpus/aarch64/venom.S 261endif 262 263else 264FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 265 lib/cpus/aarch32/cortex_a57.S \ 266 lib/cpus/aarch32/cortex_a53.S 267endif 268 269BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 270 drivers/arm/sp805/sp805.c \ 271 drivers/delay_timer/delay_timer.c \ 272 drivers/io/io_semihosting.c \ 273 lib/semihosting/semihosting.c \ 274 lib/semihosting/${ARCH}/semihosting_call.S \ 275 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 276 plat/arm/board/fvp/fvp_bl1_setup.c \ 277 plat/arm/board/fvp/fvp_cpu_pwr.c \ 278 plat/arm/board/fvp/fvp_err.c \ 279 plat/arm/board/fvp/fvp_io_storage.c \ 280 plat/arm/board/fvp/fvp_topology.c \ 281 ${FVP_CPU_LIBS} \ 282 ${FVP_INTERCONNECT_SOURCES} 283 284ifeq (${USE_SP804_TIMER},1) 285BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 286else 287BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 288endif 289 290 291BL2_SOURCES += drivers/arm/sp805/sp805.c \ 292 drivers/io/io_semihosting.c \ 293 lib/utils/mem_region.c \ 294 lib/semihosting/semihosting.c \ 295 lib/semihosting/${ARCH}/semihosting_call.S \ 296 plat/arm/board/fvp/fvp_bl2_setup.c \ 297 plat/arm/board/fvp/fvp_err.c \ 298 plat/arm/board/fvp/fvp_io_storage.c \ 299 plat/arm/common/arm_nor_psci_mem_protect.c \ 300 ${FVP_SECURITY_SOURCES} 301 302 303ifeq (${COT_DESC_IN_DTB},1) 304BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 305endif 306 307ifeq (${ENABLE_RME},1) 308BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 309 plat/arm/board/fvp/fvp_cpu_pwr.c 310 311BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 312 plat/arm/board/fvp/fvp_realm_attest_key.c \ 313 plat/arm/board/fvp/fvp_el3_token_sign.c \ 314 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 315 plat/arm/common/plat_rmm_mem_carveout.c 316endif 317 318ifneq (${ENABLE_FEAT_RNG_TRAP},0) 319BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 320endif 321 322ifeq (${RESET_TO_BL2},1) 323BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 324 plat/arm/board/fvp/fvp_cpu_pwr.c \ 325 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 326 ${FVP_CPU_LIBS} \ 327 ${FVP_INTERCONNECT_SOURCES} 328endif 329 330ifeq (${USE_SP804_TIMER},1) 331BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 332endif 333 334BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 335 ${FVP_SECURITY_SOURCES} 336 337ifeq (${USE_SP804_TIMER},1) 338BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 339endif 340 341BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 342 drivers/arm/smmu/smmu_v3.c \ 343 drivers/delay_timer/delay_timer.c \ 344 drivers/cfi/v2m/v2m_flash.c \ 345 lib/utils/mem_region.c \ 346 plat/arm/board/fvp/fvp_bl31_setup.c \ 347 plat/arm/board/fvp/fvp_console.c \ 348 plat/arm/board/fvp/fvp_pm.c \ 349 plat/arm/board/fvp/fvp_topology.c \ 350 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 351 plat/arm/board/fvp/fvp_cpu_pwr.c \ 352 plat/arm/common/arm_nor_psci_mem_protect.c \ 353 ${FVP_CPU_LIBS} \ 354 ${FVP_INTERCONNECT_SOURCES} \ 355 ${FVP_SECURITY_SOURCES} 356 357# Support for fconf in BL31 358# Added separately from the above list for better readability 359ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 360BL31_SOURCES += lib/fconf/fconf.c \ 361 lib/fconf/fconf_dyn_cfg_getter.c \ 362 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 363 364BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 365 366ifeq (${SEC_INT_DESC_IN_FCONF},1) 367BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 368endif 369 370endif 371 372ifeq (${USE_SP804_TIMER},1) 373BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 374else 375BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 376endif 377 378# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 379FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 380 381FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 382$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 383HW_CONFIG := ${FVP_HW_CONFIG} 384 385HW_CONFIG_BASE ?= 0x82000000 386 387# Set default initrd base 128MiB offset of the default kernel address in FVP 388INITRD_BASE ?= 0x90000000 389 390# Kernel base address supports Linux kernels before v5.7 391# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 392ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 393 PRELOADED_BL33_BASE ?= 0x80080000 394 ifeq (${RESET_TO_BL31},1) 395 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 396 endif 397endif 398 399ifeq (${TRANSFER_LIST}, 0) 400FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 401 ${PLAT}_fw_config.dts \ 402 ${PLAT}_tb_fw_config.dts \ 403 ${PLAT}_soc_fw_config.dts \ 404 ${PLAT}_nt_fw_config.dts \ 405 ) 406 407FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 408FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 409FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 410FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 411 412ifeq (${SPD},tspd) 413FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 414FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 415 416# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 417$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 418endif 419 420# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 421$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 422# Add the NT_FW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 424endif 425 426ifeq (${SPD},spmd) 427 428ifeq ($(ARM_SPMC_MANIFEST_DTS),) 429ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 430endif 431 432FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 433FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 434 435# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 436$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 437endif 438 439# Add the HW_CONFIG to FIP and specify the same to certtool 440$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 441 442ifeq (${TRANSFER_LIST}, 1) 443 444ifeq ($(RESET_TO_BL31), 1) 445FW_HANDOFF_SIZE := 20000 446 447TRANSFER_LIST_DTB_OFFSET := 0x20 448$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 449endif 450endif 451 452ifeq (${HOB_LIST}, 1) 453include lib/hob/hob.mk 454endif 455 456# Enable dynamic mitigation support by default 457DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 458 459ifneq (${ENABLE_FEAT_AMU},0) 460BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 461 lib/cpus/aarch64/cpuamu_helpers.S 462 463ifeq (${HW_ASSISTED_COHERENCY}, 1) 464BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 465 lib/cpus/aarch64/neoverse_n1_pubsub.c 466endif 467endif 468 469ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 470 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 471 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 472 endif 473 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 474 plat/arm/board/fvp/aarch64/fvp_ea.c 475endif 476 477ifneq (${ENABLE_STACK_PROTECTOR},0) 478PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 479endif 480 481# Enable the dynamic translation tables library. 482ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 483 ifeq (${ARCH},aarch32) 484 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 485 else # AArch64 486 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 487 endif 488endif 489 490ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 491 ifeq (${ARCH},aarch32) 492 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 493 else # AArch64 494 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 495 ifeq (${SPD},tspd) 496 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 497 endif 498 endif 499endif 500 501ifeq (${USE_DEBUGFS},1) 502 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 503endif 504 505# Add support for platform supplied linker script for BL31 build 506PLAT_EXTRA_LD_SCRIPT := 1 507 508ifneq (${RESET_TO_BL2}, 0) 509 override BL1_SOURCES = 510endif 511 512include plat/arm/board/common/board_common.mk 513include plat/arm/common/arm_common.mk 514 515ifeq (${MEASURED_BOOT},1) 516BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 517 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 518 lib/psa/measured_boot.c 519 520BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 521 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 522 lib/psa/measured_boot.c 523endif 524 525ifeq (${DRTM_SUPPORT}, 1) 526BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 527 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 528 plat/arm/board/fvp/fvp_drtm_err.c \ 529 plat/arm/board/fvp/fvp_drtm_measurement.c \ 530 plat/arm/board/fvp/fvp_drtm_stub.c \ 531 plat/arm/common/arm_dyn_cfg.c \ 532 plat/arm/board/fvp/fvp_err.c 533endif 534 535ifeq (${TRUSTED_BOARD_BOOT}, 1) 536BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 537BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 538 539# FVP being a development platform, enable capability to disable Authentication 540# dynamically if TRUSTED_BOARD_BOOT is set. 541DYN_DISABLE_AUTH := 1 542endif 543 544ifeq (${SPMC_AT_EL3}, 1) 545PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 546endif 547 548PSCI_OS_INIT_MODE := 1 549 550ifeq (${SPD},spmd) 551BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 552endif 553 554# Test specific macros, keep them at bottom of this file 555$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 556ifeq (${PLATFORM_TEST_EA_FFH}, 1) 557 ifeq (${FFH_SUPPORT}, 0) 558 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 559 endif 560 561endif 562 563PLATFORM_TEST_RAS_FFH ?= 0 564$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 565ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 566 ifeq (${ENABLE_FEAT_RAS}, 0) 567 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 568 endif 569 ifeq (${SDEI_SUPPORT}, 0) 570 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 571 endif 572 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 573 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 574 endif 575endif 576 577$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 578ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 579 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 580 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 581 endif 582 ifeq (${ENABLE_SPMD_LP}, 0) 583 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 584 endif 585 ifeq (${ENABLE_FEAT_RAS}, 0) 586 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 587 endif 588 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 589 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 590 endif 591endif 592 593ifeq (${ERRATA_ABI_SUPPORT}, 1) 594include plat/arm/board/fvp/fvp_cpu_errata.mk 595endif 596 597# Build macro necessary for running SPM tests on FVP platform 598$(eval $(call add_define,PLAT_TEST_SPM)) 599 600ifeq (${LFA_SUPPORT},1) 601BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 602endif 603 604# This is set to 1 by default when the firmware update 605# support is enabled. Since the BL2 image is not updatable 606ifeq ($(PSA_FWU_SUPPORT),1) 607 SEPARATE_BL2_FIP := 1 608endif 609 610ifeq (${TRANSFER_LIST}, 0) 611ifeq (${SEPARATE_BL2_FIP},1) 612$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 613$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 614else 615$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 616$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 617endif 618endif 619