1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50endif 51endif 52 53 ENABLE_BRBE_FOR_NS := 2 54 ENABLE_TRBE_FOR_NS := 2 55endif 56 57ENABLE_SYS_REG_TRACE_FOR_NS := 2 58ENABLE_FEAT_CSV2_2 := 2 59ENABLE_FEAT_CSV2_3 := 2 60ENABLE_FEAT_DEBUGV8P9 := 2 61ENABLE_FEAT_DIT := 2 62ENABLE_FEAT_PAN := 2 63ENABLE_FEAT_VHE := 2 64CTX_INCLUDE_NEVE_REGS := 2 65ENABLE_FEAT_SEL2 := 2 66ENABLE_TRF_FOR_NS := 2 67ENABLE_FEAT_ECV := 2 68ENABLE_FEAT_FGT := 2 69ENABLE_FEAT_FGT2 := 2 70ENABLE_FEAT_TCR2 := 2 71ENABLE_FEAT_S2PIE := 2 72ENABLE_FEAT_S1PIE := 2 73ENABLE_FEAT_S2POE := 2 74ENABLE_FEAT_S1POE := 2 75 76# The FVP platform depends on this macro to build with correct GIC driver. 77$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 78 79# Pass FVP_CLUSTER_COUNT to the build system. 80$(eval $(call add_define,FVP_CLUSTER_COUNT)) 81 82# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 83$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 84 85# Pass FVP_MAX_PE_PER_CPU to the build system. 86$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 87 88# Pass FVP_GICR_REGION_PROTECTION to the build system. 89$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 90 91# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 92$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 93 94# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 95# choose the CCI driver , else the CCN driver 96ifeq ($(FVP_CLUSTER_COUNT), 0) 97$(error "Incorrect cluster count specified for FVP port") 98else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 99FVP_INTERCONNECT_DRIVER := FVP_CCI 100else 101FVP_INTERCONNECT_DRIVER := FVP_CCN 102endif 103 104$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 105 106# Choose the GIC sources depending upon the how the FVP will be invoked 107ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 108 109# The GIC model (GIC-600 or GIC-500) will be detected at runtime 110GICV3_SUPPORT_GIC600 := 1 111GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 112 113# Include GICv3 driver files 114include drivers/arm/gic/v3/gicv3.mk 115 116FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 117 plat/common/plat_gicv3.c \ 118 plat/arm/common/arm_gicv3.c 119 120 ifeq ($(filter 1,${RESET_TO_BL2} \ 121 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 122 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 123 endif 124 125else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 126 127# No GICv4 extension 128GIC_ENABLE_V4_EXTN := 0 129$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 130 131# Include GICv2 driver files 132include drivers/arm/gic/v2/gicv2.mk 133 134FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 135 plat/common/plat_gicv2.c \ 136 plat/arm/common/arm_gicv2.c 137 138FVP_DT_PREFIX := fvp-base-gicv2-psci 139else 140$(error "Incorrect GIC driver chosen on FVP port") 141endif 142 143ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 144FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 145else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 146FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 147 plat/arm/common/arm_ccn.c 148else 149$(error "Incorrect CCN driver chosen on FVP port") 150endif 151 152FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 153 plat/arm/board/fvp/fvp_security.c \ 154 plat/arm/common/arm_tzc400.c 155 156 157PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 158 -Iinclude/lib/psa 159 160 161PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 162 163FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 164 165ifeq (${ARCH}, aarch64) 166 167# select a different set of CPU files, depending on whether we compile for 168# hardware assisted coherency cores or not 169ifeq (${HW_ASSISTED_COHERENCY}, 0) 170# Cores used without DSU 171 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 172 lib/cpus/aarch64/cortex_a53.S \ 173 lib/cpus/aarch64/cortex_a57.S \ 174 lib/cpus/aarch64/cortex_a72.S \ 175 lib/cpus/aarch64/cortex_a73.S 176else 177# Cores used with DSU only 178 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 179 # AArch64-only cores 180 # TODO: add all cores to the appropriate lists 181 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 182 lib/cpus/aarch64/cortex_a65ae.S \ 183 lib/cpus/aarch64/cortex_a76.S \ 184 lib/cpus/aarch64/cortex_a76ae.S \ 185 lib/cpus/aarch64/cortex_a77.S \ 186 lib/cpus/aarch64/cortex_a78.S \ 187 lib/cpus/aarch64/cortex_a78_ae.S \ 188 lib/cpus/aarch64/cortex_a78c.S \ 189 lib/cpus/aarch64/cortex_a710.S \ 190 lib/cpus/aarch64/cortex_a715.S \ 191 lib/cpus/aarch64/cortex_a720.S \ 192 lib/cpus/aarch64/neoverse_n_common.S \ 193 lib/cpus/aarch64/neoverse_n1.S \ 194 lib/cpus/aarch64/neoverse_n2.S \ 195 lib/cpus/aarch64/neoverse_v1.S \ 196 lib/cpus/aarch64/neoverse_e1.S \ 197 lib/cpus/aarch64/cortex_x2.S \ 198 lib/cpus/aarch64/cortex_x4.S 199 endif 200 # AArch64/AArch32 cores 201 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 202 lib/cpus/aarch64/cortex_a75.S 203endif 204 205#Build AArch64-only CPUs with no FVP model yet. 206ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 207 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 208 lib/cpus/aarch64/cortex_gelas.S \ 209 lib/cpus/aarch64/nevis.S \ 210 lib/cpus/aarch64/travis.S 211endif 212 213else 214FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 215 lib/cpus/aarch32/cortex_a57.S \ 216 lib/cpus/aarch32/cortex_a53.S 217endif 218 219BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 220 drivers/arm/sp805/sp805.c \ 221 drivers/delay_timer/delay_timer.c \ 222 drivers/io/io_semihosting.c \ 223 lib/semihosting/semihosting.c \ 224 lib/semihosting/${ARCH}/semihosting_call.S \ 225 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 226 plat/arm/board/fvp/fvp_bl1_setup.c \ 227 plat/arm/board/fvp/fvp_cpu_pwr.c \ 228 plat/arm/board/fvp/fvp_err.c \ 229 plat/arm/board/fvp/fvp_io_storage.c \ 230 plat/arm/board/fvp/fvp_topology.c \ 231 ${FVP_CPU_LIBS} \ 232 ${FVP_INTERCONNECT_SOURCES} 233 234ifeq (${USE_SP804_TIMER},1) 235BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 236else 237BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 238endif 239 240 241BL2_SOURCES += drivers/arm/sp805/sp805.c \ 242 drivers/io/io_semihosting.c \ 243 lib/utils/mem_region.c \ 244 lib/semihosting/semihosting.c \ 245 lib/semihosting/${ARCH}/semihosting_call.S \ 246 plat/arm/board/fvp/fvp_bl2_setup.c \ 247 plat/arm/board/fvp/fvp_err.c \ 248 plat/arm/board/fvp/fvp_io_storage.c \ 249 plat/arm/common/arm_nor_psci_mem_protect.c \ 250 ${FVP_SECURITY_SOURCES} 251 252 253ifeq (${COT_DESC_IN_DTB},1) 254BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 255endif 256 257ifeq (${ENABLE_RME},1) 258BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 259 plat/arm/board/fvp/fvp_cpu_pwr.c 260 261BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 262 plat/arm/board/fvp/fvp_realm_attest_key.c 263endif 264 265ifeq (${ENABLE_FEAT_RNG_TRAP},1) 266BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 267endif 268 269ifeq (${RESET_TO_BL2},1) 270BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 271 plat/arm/board/fvp/fvp_cpu_pwr.c \ 272 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 273 ${FVP_CPU_LIBS} \ 274 ${FVP_INTERCONNECT_SOURCES} 275endif 276 277ifeq (${USE_SP804_TIMER},1) 278BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 279endif 280 281BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 282 ${FVP_SECURITY_SOURCES} 283 284ifeq (${USE_SP804_TIMER},1) 285BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 286endif 287 288BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 289 drivers/arm/smmu/smmu_v3.c \ 290 drivers/delay_timer/delay_timer.c \ 291 drivers/cfi/v2m/v2m_flash.c \ 292 lib/utils/mem_region.c \ 293 plat/arm/board/fvp/fvp_bl31_setup.c \ 294 plat/arm/board/fvp/fvp_console.c \ 295 plat/arm/board/fvp/fvp_pm.c \ 296 plat/arm/board/fvp/fvp_topology.c \ 297 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 298 plat/arm/board/fvp/fvp_cpu_pwr.c \ 299 plat/arm/common/arm_nor_psci_mem_protect.c \ 300 ${FVP_CPU_LIBS} \ 301 ${FVP_GIC_SOURCES} \ 302 ${FVP_INTERCONNECT_SOURCES} \ 303 ${FVP_SECURITY_SOURCES} 304 305# Support for fconf in BL31 306# Added separately from the above list for better readability 307ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 308BL31_SOURCES += lib/fconf/fconf.c \ 309 lib/fconf/fconf_dyn_cfg_getter.c \ 310 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 311 312BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 313 314ifeq (${SEC_INT_DESC_IN_FCONF},1) 315BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 316endif 317 318endif 319 320ifeq (${USE_SP804_TIMER},1) 321BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 322else 323BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 324endif 325 326ifeq (${TRANSFER_LIST}, 1) 327include lib/transfer_list/transfer_list.mk 328endif 329 330# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 331ifdef UNIX_MK 332FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 333FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 334 335FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 336$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 337 338ifeq (${TRANSFER_LIST}, 1) 339FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 340 ${PLAT}_tb_fw_config.dts \ 341 ) 342else 343FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 344 ${PLAT}_fw_config.dts \ 345 ${PLAT}_tb_fw_config.dts \ 346 ${PLAT}_soc_fw_config.dts \ 347 ${PLAT}_nt_fw_config.dts \ 348 ) 349 350FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 351FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 352FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 353 354ifeq (${SPD},tspd) 355FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 356FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 357 358# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 359$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 360endif 361 362ifeq (${SPD},spmd) 363 364ifeq ($(ARM_SPMC_MANIFEST_DTS),) 365ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 366endif 367 368FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 369FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 370 371# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 373endif 374 375# Add the FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 377# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 379# Add the NT_FW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 381endif 382 383# Add the TB_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 385# Add the HW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 387endif 388 389# Enable dynamic mitigation support by default 390DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 391 392ifneq (${ENABLE_FEAT_AMU},0) 393BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 394 lib/cpus/aarch64/cpuamu_helpers.S 395 396ifeq (${HW_ASSISTED_COHERENCY}, 1) 397BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 398 lib/cpus/aarch64/neoverse_n1_pubsub.c 399endif 400endif 401 402ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 403 ifeq (${ENABLE_FEAT_RAS},1) 404 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 405 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 406 else 407 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 408 endif 409 else 410 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 411 endif 412endif 413 414ifneq (${ENABLE_STACK_PROTECTOR},0) 415PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 416endif 417 418# Enable the dynamic translation tables library. 419ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 420 ifeq (${ARCH},aarch32) 421 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 422 else # AArch64 423 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 424 endif 425endif 426 427ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 428 ifeq (${ARCH},aarch32) 429 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 430 else # AArch64 431 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 432 ifeq (${SPD},tspd) 433 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 434 endif 435 endif 436endif 437 438ifeq (${USE_DEBUGFS},1) 439 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 440endif 441 442# Add support for platform supplied linker script for BL31 build 443$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 444 445ifneq (${RESET_TO_BL2}, 0) 446 override BL1_SOURCES = 447endif 448 449include plat/arm/board/common/board_common.mk 450include plat/arm/common/arm_common.mk 451 452ifeq (${MEASURED_BOOT},1) 453BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 454 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 455 lib/psa/measured_boot.c 456 457BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 458 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 459 lib/psa/measured_boot.c 460endif 461 462ifeq (${DRTM_SUPPORT}, 1) 463BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 464 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 465 plat/arm/board/fvp/fvp_drtm_err.c \ 466 plat/arm/board/fvp/fvp_drtm_measurement.c \ 467 plat/arm/board/fvp/fvp_drtm_stub.c \ 468 plat/arm/common/arm_dyn_cfg.c \ 469 plat/arm/board/fvp/fvp_err.c 470endif 471 472ifeq (${TRUSTED_BOARD_BOOT}, 1) 473BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 474BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 475 476# FVP being a development platform, enable capability to disable Authentication 477# dynamically if TRUSTED_BOARD_BOOT is set. 478DYN_DISABLE_AUTH := 1 479endif 480 481ifeq (${SPMC_AT_EL3}, 1) 482PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 483endif 484 485PSCI_OS_INIT_MODE := 1 486 487ifeq (${SPD},spmd) 488BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 489endif 490 491# Test specific macros, keep them at bottom of this file 492$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 493ifeq (${PLATFORM_TEST_EA_FFH}, 1) 494 ifeq (${FFH_SUPPORT}, 0) 495 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 496 endif 497 498endif 499 500$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 501ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 502 ifeq (${ENABLE_FEAT_RAS}, 0) 503 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 504 endif 505 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 506 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 507 endif 508endif 509 510$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 511ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 512 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 513 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 514 endif 515 ifeq (${ENABLE_SPMD_LP}, 0) 516 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 517 endif 518 ifeq (${ENABLE_FEAT_RAS}, 0) 519 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 520 endif 521 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 522 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 523 endif 524endif 525 526ifeq (${ERRATA_ABI_SUPPORT}, 1) 527include plat/arm/board/fvp/fvp_cpu_errata.mk 528endif 529 530# Build macro necessary for running SPM tests on FVP platform 531$(eval $(call add_define,PLAT_TEST_SPM)) 532