1# 2# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Use the SP804 timer instead of the generic one 11FVP_USE_SP804_TIMER := 0 12 13# Default cluster count for FVP 14FVP_CLUSTER_COUNT := 2 15 16# Default number of CPUs per cluster on FVP 17FVP_MAX_CPUS_PER_CLUSTER := 4 18 19# Default number of threads per CPU on FVP 20FVP_MAX_PE_PER_CPU := 1 21 22FVP_DT_PREFIX := fvp-base-gicv3-psci 23 24$(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) 25$(eval $(call add_define,FVP_USE_SP804_TIMER)) 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 40# choose the CCI driver , else the CCN driver 41ifeq ($(FVP_CLUSTER_COUNT), 0) 42$(error "Incorrect cluster count specified for FVP port") 43else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 44FVP_INTERCONNECT_DRIVER := FVP_CCI 45else 46FVP_INTERCONNECT_DRIVER := FVP_CCN 47endif 48 49$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 50 51# Choose the GIC sources depending upon the how the FVP will be invoked 52ifeq (${FVP_USE_GIC_DRIVER},$(filter ${FVP_USE_GIC_DRIVER},FVP_GICV3 FVP_GIC600)) 53 54 # GIC500 is the default option in case GICV3_IMPL is not set 55 ifeq (${FVP_USE_GIC_DRIVER}, FVP_GIC600) 56 GICV3_IMPL := GIC600 57 endif 58 59GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 60 61# Include GICv3 driver files 62include drivers/arm/gic/v3/gicv3.mk 63 64FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 65 plat/common/plat_gicv3.c \ 66 plat/arm/common/arm_gicv3.c 67 68else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 69 70# No GICv4 extension 71GIC_ENABLE_V4_EXTN := 0 72$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 73 74# No support for extended PPI and SPI range 75GIC_EXT_INTID := 0 76$(eval $(call add_define,GIC_EXT_INTID)) 77 78FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 79 drivers/arm/gic/v2/gicv2_main.c \ 80 drivers/arm/gic/v2/gicv2_helpers.c \ 81 plat/common/plat_gicv2.c \ 82 plat/arm/common/arm_gicv2.c 83 84FVP_DT_PREFIX := fvp-base-gicv2-psci 85else 86$(error "Incorrect GIC driver chosen on FVP port") 87endif 88 89ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 90FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 91else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 92FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 93 plat/arm/common/arm_ccn.c 94else 95$(error "Incorrect CCN driver chosen on FVP port") 96endif 97 98FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 99 plat/arm/board/fvp/fvp_security.c \ 100 plat/arm/common/arm_tzc400.c 101 102 103PLAT_INCLUDES := -Iplat/arm/board/fvp/include 104 105 106PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 107 108FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 109 110ifeq (${ARCH}, aarch64) 111 112# select a different set of CPU files, depending on whether we compile for 113# hardware assisted coherency cores or not 114ifeq (${HW_ASSISTED_COHERENCY}, 0) 115# Cores used without DSU 116 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 117 lib/cpus/aarch64/cortex_a53.S \ 118 lib/cpus/aarch64/cortex_a57.S \ 119 lib/cpus/aarch64/cortex_a72.S \ 120 lib/cpus/aarch64/cortex_a73.S 121else 122# Cores used with DSU only 123 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 124 # AArch64-only cores 125 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 126 lib/cpus/aarch64/cortex_a76ae.S \ 127 lib/cpus/aarch64/cortex_a77.S \ 128 lib/cpus/aarch64/neoverse_n1.S \ 129 lib/cpus/aarch64/neoverse_e1.S \ 130 lib/cpus/aarch64/neoverse_zeus.S \ 131 lib/cpus/aarch64/cortex_hercules.S \ 132 lib/cpus/aarch64/cortex_hercules_ae.S \ 133 lib/cpus/aarch64/cortex_klein.S \ 134 lib/cpus/aarch64/cortex_matterhorn.S \ 135 lib/cpus/aarch64/cortex_a65.S \ 136 lib/cpus/aarch64/cortex_a65ae.S 137 endif 138 # AArch64/AArch32 cores 139 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 140 lib/cpus/aarch64/cortex_a75.S 141endif 142 143else 144FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 145endif 146 147BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 148 drivers/arm/sp805/sp805.c \ 149 drivers/delay_timer/delay_timer.c \ 150 drivers/io/io_semihosting.c \ 151 lib/semihosting/semihosting.c \ 152 lib/semihosting/${ARCH}/semihosting_call.S \ 153 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 154 plat/arm/board/fvp/fvp_bl1_setup.c \ 155 plat/arm/board/fvp/fvp_err.c \ 156 plat/arm/board/fvp/fvp_io_storage.c \ 157 ${FVP_CPU_LIBS} \ 158 ${FVP_INTERCONNECT_SOURCES} 159 160ifeq (${FVP_USE_SP804_TIMER},1) 161BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 162else 163BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 164endif 165 166 167BL2_SOURCES += drivers/arm/sp805/sp805.c \ 168 drivers/io/io_semihosting.c \ 169 lib/utils/mem_region.c \ 170 lib/semihosting/semihosting.c \ 171 lib/semihosting/${ARCH}/semihosting_call.S \ 172 plat/arm/board/fvp/fvp_bl2_setup.c \ 173 plat/arm/board/fvp/fvp_err.c \ 174 plat/arm/board/fvp/fvp_io_storage.c \ 175 plat/arm/common/arm_nor_psci_mem_protect.c \ 176 ${FVP_SECURITY_SOURCES} 177 178 179 180ifeq (${BL2_AT_EL3},1) 181BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 182 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 183 ${FVP_CPU_LIBS} \ 184 ${FVP_INTERCONNECT_SOURCES} 185endif 186 187ifeq (${FVP_USE_SP804_TIMER},1) 188BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 189endif 190 191BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 192 ${FVP_SECURITY_SOURCES} 193 194ifeq (${FVP_USE_SP804_TIMER},1) 195BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 196endif 197 198BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 199 drivers/arm/smmu/smmu_v3.c \ 200 drivers/delay_timer/delay_timer.c \ 201 drivers/cfi/v2m/v2m_flash.c \ 202 lib/utils/mem_region.c \ 203 plat/arm/board/fvp/fvp_bl31_setup.c \ 204 plat/arm/board/fvp/fvp_console.c \ 205 plat/arm/board/fvp/fvp_pm.c \ 206 plat/arm/board/fvp/fvp_topology.c \ 207 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 208 plat/arm/common/arm_nor_psci_mem_protect.c \ 209 ${FVP_CPU_LIBS} \ 210 ${FVP_GIC_SOURCES} \ 211 ${FVP_INTERCONNECT_SOURCES} \ 212 ${FVP_SECURITY_SOURCES} 213 214# Support for fconf in BL31 215# Added separately from the above list for better readability 216ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 217BL31_SOURCES += common/fdt_wrappers.c \ 218 lib/fconf/fconf.c \ 219 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 220endif 221 222ifeq (${FVP_USE_SP804_TIMER},1) 223BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 224else 225BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 226endif 227 228# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 229ifdef UNIX_MK 230FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 231FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 232 ${PLAT}_fw_config.dts \ 233 ${PLAT}_soc_fw_config.dts \ 234 ${PLAT}_nt_fw_config.dts \ 235 ) 236 237FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 238FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 239FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 240 241ifeq (${SPD},tspd) 242FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 243FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 244 245# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 246$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 247endif 248 249ifeq (${SPD},spmd) 250FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 251FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_spmc_manifest.dtb 252 253# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 254$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 255endif 256 257# Add the TB_FW_CONFIG to FIP and specify the same to certtool 258$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) 259# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 260$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config)) 261# Add the NT_FW_CONFIG to FIP and specify the same to certtool 262$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config)) 263 264FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 265$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 266 267# Add the HW_CONFIG to FIP and specify the same to certtool 268$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) 269endif 270 271# Enable Activity Monitor Unit extensions by default 272ENABLE_AMU := 1 273 274# Enable dynamic mitigation support by default 275DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 276 277# Enable reclaiming of BL31 initialisation code for secondary cores 278# stacks for FVP. However, don't enable reclaiming for clang. 279ifneq (${RESET_TO_BL31},1) 280ifeq ($(findstring clang,$(notdir $(CC))),) 281RECLAIM_INIT_CODE := 1 282endif 283endif 284 285ifeq (${ENABLE_AMU},1) 286BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 287 lib/cpus/aarch64/cpuamu_helpers.S 288 289ifeq (${HW_ASSISTED_COHERENCY}, 1) 290BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 291 lib/cpus/aarch64/neoverse_n1_pubsub.c 292endif 293endif 294 295ifeq (${RAS_EXTENSION},1) 296BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 297endif 298 299ifneq (${ENABLE_STACK_PROTECTOR},0) 300PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 301endif 302 303ifeq (${ARCH},aarch32) 304 NEED_BL32 := yes 305endif 306 307# Enable the dynamic translation tables library. 308ifeq (${ARCH},aarch32) 309 ifeq (${RESET_TO_SP_MIN},1) 310 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 311 endif 312else # AArch64 313 ifeq (${RESET_TO_BL31},1) 314 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 315 endif 316 ifeq (${SPD},trusty) 317 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 318 endif 319endif 320 321ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 322 ifeq (${ARCH},aarch32) 323 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 324 else # AArch64 325 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 326 ifeq (${SPD},tspd) 327 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 328 endif 329 endif 330endif 331 332ifeq (${USE_DEBUGFS},1) 333 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 334endif 335 336# Add support for platform supplied linker script for BL31 build 337$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 338 339ifneq (${BL2_AT_EL3}, 0) 340 override BL1_SOURCES = 341endif 342 343include plat/arm/board/common/board_common.mk 344include plat/arm/common/arm_common.mk 345 346ifeq (${TRUSTED_BOARD_BOOT}, 1) 347BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 348BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 349# FVP being a development platform, enable capability to disable Authentication 350# dynamically if TRUSTED_BOARD_BOOT is set. 351DYN_DISABLE_AUTH := 1 352endif 353