1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59 ENABLE_FEAT_D128 := 2 60 ENABLE_FEAT_FPMR := 2 61endif 62 63ENABLE_SYS_REG_TRACE_FOR_NS := 2 64ENABLE_FEAT_CSV2_2 := 2 65ENABLE_FEAT_CSV2_3 := 2 66ENABLE_FEAT_DEBUGV8P9 := 2 67ENABLE_FEAT_DIT := 2 68ENABLE_FEAT_PAN := 2 69ENABLE_FEAT_VHE := 2 70CTX_INCLUDE_NEVE_REGS := 2 71ENABLE_FEAT_SEL2 := 2 72ENABLE_TRF_FOR_NS := 2 73ENABLE_FEAT_ECV := 2 74ENABLE_FEAT_FGT := 2 75ENABLE_FEAT_FGT2 := 2 76ENABLE_FEAT_THE := 2 77ENABLE_FEAT_TCR2 := 2 78ENABLE_FEAT_S2PIE := 2 79ENABLE_FEAT_S1PIE := 2 80ENABLE_FEAT_S2POE := 2 81ENABLE_FEAT_S1POE := 2 82ENABLE_FEAT_SCTLR2 := 2 83ENABLE_FEAT_MTE2 := 2 84ENABLE_FEAT_LS64_ACCDATA := 2 85 86# The FVP platform depends on this macro to build with correct GIC driver. 87$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 88 89# Pass FVP_CLUSTER_COUNT to the build system. 90$(eval $(call add_define,FVP_CLUSTER_COUNT)) 91 92# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 93$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 94 95# Pass FVP_MAX_PE_PER_CPU to the build system. 96$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 97 98# Pass FVP_GICR_REGION_PROTECTION to the build system. 99$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 100 101# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 102$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 103 104# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 105# choose the CCI driver , else the CCN driver 106ifeq ($(FVP_CLUSTER_COUNT), 0) 107$(error "Incorrect cluster count specified for FVP port") 108else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 109FVP_INTERCONNECT_DRIVER := FVP_CCI 110else 111FVP_INTERCONNECT_DRIVER := FVP_CCN 112endif 113 114$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 115 116# Choose the GIC sources depending upon the how the FVP will be invoked 117ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 118 119# The GIC model (GIC-600 or GIC-500) will be detected at runtime 120GICV3_SUPPORT_GIC600 := 1 121GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 122 123# Include GICv3 driver files 124include drivers/arm/gic/v3/gicv3.mk 125 126FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 127 plat/common/plat_gicv3.c \ 128 plat/arm/common/arm_gicv3.c 129 130 ifeq ($(filter 1,${RESET_TO_BL2} \ 131 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 132 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 133 endif 134 135else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 136 137# No GICv4 extension 138GIC_ENABLE_V4_EXTN := 0 139$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 140 141# Include GICv2 driver files 142include drivers/arm/gic/v2/gicv2.mk 143 144FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 145 plat/common/plat_gicv2.c \ 146 plat/arm/common/arm_gicv2.c 147 148FVP_DT_PREFIX := fvp-base-gicv2-psci 149else 150$(error "Incorrect GIC driver chosen on FVP port") 151endif 152 153ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 154FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 155else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 156FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 157 plat/arm/common/arm_ccn.c 158else 159$(error "Incorrect CCN driver chosen on FVP port") 160endif 161 162FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 163 plat/arm/board/fvp/fvp_security.c \ 164 plat/arm/common/arm_tzc400.c 165 166 167PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 168 -Iinclude/lib/psa 169 170 171PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 172 173FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 174 175ifeq (${ARCH}, aarch64) 176 177# select a different set of CPU files, depending on whether we compile for 178# hardware assisted coherency cores or not 179ifeq (${HW_ASSISTED_COHERENCY}, 0) 180# Cores used without DSU 181 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 182 lib/cpus/aarch64/cortex_a53.S \ 183 lib/cpus/aarch64/cortex_a57.S \ 184 lib/cpus/aarch64/cortex_a72.S \ 185 lib/cpus/aarch64/cortex_a73.S 186else 187# Cores used with DSU only 188 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 189 # AArch64-only cores 190 # TODO: add all cores to the appropriate lists 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 192 lib/cpus/aarch64/cortex_a65ae.S \ 193 lib/cpus/aarch64/cortex_a76.S \ 194 lib/cpus/aarch64/cortex_a76ae.S \ 195 lib/cpus/aarch64/cortex_a77.S \ 196 lib/cpus/aarch64/cortex_a78.S \ 197 lib/cpus/aarch64/cortex_a78_ae.S \ 198 lib/cpus/aarch64/cortex_a78c.S \ 199 lib/cpus/aarch64/cortex_a710.S \ 200 lib/cpus/aarch64/cortex_a715.S \ 201 lib/cpus/aarch64/cortex_a720.S \ 202 lib/cpus/aarch64/cortex_a720_ae.S \ 203 lib/cpus/aarch64/neoverse_n_common.S \ 204 lib/cpus/aarch64/neoverse_n1.S \ 205 lib/cpus/aarch64/neoverse_n2.S \ 206 lib/cpus/aarch64/neoverse_v1.S \ 207 lib/cpus/aarch64/neoverse_e1.S \ 208 lib/cpus/aarch64/cortex_x2.S \ 209 lib/cpus/aarch64/cortex_x4.S 210 endif 211 # AArch64/AArch32 cores 212 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 213 lib/cpus/aarch64/cortex_a75.S 214endif 215 216#Build AArch64-only CPUs with no FVP model yet. 217ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 218 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 219 lib/cpus/aarch64/cortex_gelas.S \ 220 lib/cpus/aarch64/nevis.S \ 221 lib/cpus/aarch64/travis.S \ 222 lib/cpus/aarch64/cortex_arcadia.S \ 223 lib/cpus/aarch64/cortex_alto.S 224endif 225 226else 227FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 228 lib/cpus/aarch32/cortex_a57.S \ 229 lib/cpus/aarch32/cortex_a53.S 230endif 231 232BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 233 drivers/arm/sp805/sp805.c \ 234 drivers/delay_timer/delay_timer.c \ 235 drivers/io/io_semihosting.c \ 236 lib/semihosting/semihosting.c \ 237 lib/semihosting/${ARCH}/semihosting_call.S \ 238 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 239 plat/arm/board/fvp/fvp_bl1_setup.c \ 240 plat/arm/board/fvp/fvp_cpu_pwr.c \ 241 plat/arm/board/fvp/fvp_err.c \ 242 plat/arm/board/fvp/fvp_io_storage.c \ 243 plat/arm/board/fvp/fvp_topology.c \ 244 ${FVP_CPU_LIBS} \ 245 ${FVP_INTERCONNECT_SOURCES} 246 247ifeq (${USE_SP804_TIMER},1) 248BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 249else 250BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 251endif 252 253 254BL2_SOURCES += drivers/arm/sp805/sp805.c \ 255 drivers/io/io_semihosting.c \ 256 lib/utils/mem_region.c \ 257 lib/semihosting/semihosting.c \ 258 lib/semihosting/${ARCH}/semihosting_call.S \ 259 plat/arm/board/fvp/fvp_bl2_setup.c \ 260 plat/arm/board/fvp/fvp_err.c \ 261 plat/arm/board/fvp/fvp_io_storage.c \ 262 plat/arm/common/arm_nor_psci_mem_protect.c \ 263 ${FVP_SECURITY_SOURCES} 264 265 266ifeq (${COT_DESC_IN_DTB},1) 267BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 268endif 269 270ifeq (${ENABLE_RME},1) 271BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 272 plat/arm/board/fvp/fvp_cpu_pwr.c 273 274BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 275 plat/arm/board/fvp/fvp_realm_attest_key.c \ 276 plat/arm/board/fvp/fvp_el3_token_sign.c 277endif 278 279ifeq (${ENABLE_FEAT_RNG_TRAP},1) 280BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 281endif 282 283ifeq (${RESET_TO_BL2},1) 284BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 285 plat/arm/board/fvp/fvp_cpu_pwr.c \ 286 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 287 ${FVP_CPU_LIBS} \ 288 ${FVP_INTERCONNECT_SOURCES} 289endif 290 291ifeq (${USE_SP804_TIMER},1) 292BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 293endif 294 295BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 296 ${FVP_SECURITY_SOURCES} 297 298ifeq (${USE_SP804_TIMER},1) 299BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 300endif 301 302BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 303 drivers/arm/smmu/smmu_v3.c \ 304 drivers/delay_timer/delay_timer.c \ 305 drivers/cfi/v2m/v2m_flash.c \ 306 lib/utils/mem_region.c \ 307 plat/arm/board/fvp/fvp_bl31_setup.c \ 308 plat/arm/board/fvp/fvp_console.c \ 309 plat/arm/board/fvp/fvp_pm.c \ 310 plat/arm/board/fvp/fvp_topology.c \ 311 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 312 plat/arm/board/fvp/fvp_cpu_pwr.c \ 313 plat/arm/common/arm_nor_psci_mem_protect.c \ 314 ${FVP_CPU_LIBS} \ 315 ${FVP_GIC_SOURCES} \ 316 ${FVP_INTERCONNECT_SOURCES} \ 317 ${FVP_SECURITY_SOURCES} 318 319# Support for fconf in BL31 320# Added separately from the above list for better readability 321ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 322BL31_SOURCES += lib/fconf/fconf.c \ 323 lib/fconf/fconf_dyn_cfg_getter.c \ 324 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 325 326BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 327 328ifeq (${SEC_INT_DESC_IN_FCONF},1) 329BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 330endif 331 332endif 333 334ifeq (${USE_SP804_TIMER},1) 335BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 336else 337BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 338endif 339 340# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 341ifdef UNIX_MK 342FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 343 344FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 345$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 346 347ifeq (${TRANSFER_LIST}, 0) 348FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 349 ${PLAT}_fw_config.dts \ 350 ${PLAT}_tb_fw_config.dts \ 351 ${PLAT}_soc_fw_config.dts \ 352 ${PLAT}_nt_fw_config.dts \ 353 ) 354 355FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 356FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 357FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 358FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 359 360ifeq (${SPD},tspd) 361FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 362FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 363 364# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 366endif 367 368ifeq (${SPD},spmd) 369 370ifeq ($(ARM_SPMC_MANIFEST_DTS),) 371ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 372endif 373 374FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 375FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 376 377# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 379endif 380 381# Add the FW_CONFIG to FIP and specify the same to certtool 382$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 383# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 385# Add the NT_FW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 387# Add the TB_FW_CONFIG to FIP and specify the same to certtool 388$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 389endif 390 391# Add the HW_CONFIG to FIP and specify the same to certtool 392$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 393endif 394 395ifeq (${TRANSFER_LIST}, 1) 396include lib/transfer_list/transfer_list.mk 397 398ifeq ($(RESET_TO_BL31), 1) 399HW_CONFIG := ${FVP_HW_CONFIG} 400FW_HANDOFF_SIZE := 20000 401 402TRANSFER_LIST_DTB_OFFSET := 0x20 403$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 404endif 405endif 406 407ifeq (${HOB_LIST}, 1) 408include lib/hob/hob.mk 409endif 410 411# Enable dynamic mitigation support by default 412DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 413 414ifneq (${ENABLE_FEAT_AMU},0) 415BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 416 lib/cpus/aarch64/cpuamu_helpers.S 417 418ifeq (${HW_ASSISTED_COHERENCY}, 1) 419BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 420 lib/cpus/aarch64/neoverse_n1_pubsub.c 421endif 422endif 423 424ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 425 ifeq (${ENABLE_FEAT_RAS},1) 426 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 427 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 428 else 429 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 430 endif 431 else 432 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 433 endif 434endif 435 436ifneq (${ENABLE_STACK_PROTECTOR},0) 437PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 438endif 439 440# Enable the dynamic translation tables library. 441ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 442 ifeq (${ARCH},aarch32) 443 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 444 else # AArch64 445 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 446 endif 447endif 448 449ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 450 ifeq (${ARCH},aarch32) 451 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 452 else # AArch64 453 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 454 ifeq (${SPD},tspd) 455 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 456 endif 457 endif 458endif 459 460ifeq (${USE_DEBUGFS},1) 461 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 462endif 463 464# Add support for platform supplied linker script for BL31 build 465$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 466 467ifneq (${RESET_TO_BL2}, 0) 468 override BL1_SOURCES = 469endif 470 471include plat/arm/board/common/board_common.mk 472include plat/arm/common/arm_common.mk 473 474ifeq (${MEASURED_BOOT},1) 475BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 476 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 477 lib/psa/measured_boot.c 478 479BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 480 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 481 lib/psa/measured_boot.c 482endif 483 484ifeq (${DRTM_SUPPORT}, 1) 485BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 486 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 487 plat/arm/board/fvp/fvp_drtm_err.c \ 488 plat/arm/board/fvp/fvp_drtm_measurement.c \ 489 plat/arm/board/fvp/fvp_drtm_stub.c \ 490 plat/arm/common/arm_dyn_cfg.c \ 491 plat/arm/board/fvp/fvp_err.c 492endif 493 494ifeq (${TRUSTED_BOARD_BOOT}, 1) 495BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 496BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 497 498# FVP being a development platform, enable capability to disable Authentication 499# dynamically if TRUSTED_BOARD_BOOT is set. 500DYN_DISABLE_AUTH := 1 501endif 502 503ifeq (${SPMC_AT_EL3}, 1) 504PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 505endif 506 507PSCI_OS_INIT_MODE := 1 508 509ifeq (${SPD},spmd) 510BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 511endif 512 513# Test specific macros, keep them at bottom of this file 514$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 515ifeq (${PLATFORM_TEST_EA_FFH}, 1) 516 ifeq (${FFH_SUPPORT}, 0) 517 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 518 endif 519 520endif 521 522$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 523ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 524 ifeq (${ENABLE_FEAT_RAS}, 0) 525 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 526 endif 527 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 528 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 529 endif 530endif 531 532$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 533ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 534 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 535 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 536 endif 537 ifeq (${ENABLE_SPMD_LP}, 0) 538 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 539 endif 540 ifeq (${ENABLE_FEAT_RAS}, 0) 541 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 542 endif 543 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 544 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 545 endif 546endif 547 548ifeq (${ERRATA_ABI_SUPPORT}, 1) 549include plat/arm/board/fvp/fvp_cpu_errata.mk 550endif 551 552# Build macro necessary for running SPM tests on FVP platform 553$(eval $(call add_define,PLAT_TEST_SPM)) 554