1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50endif 51endif 52 53 ENABLE_BRBE_FOR_NS := 2 54 ENABLE_TRBE_FOR_NS := 2 55endif 56 57ENABLE_SYS_REG_TRACE_FOR_NS := 2 58ENABLE_FEAT_CSV2_2 := 2 59ENABLE_FEAT_CSV2_3 := 2 60ENABLE_FEAT_DIT := 2 61ENABLE_FEAT_PAN := 2 62ENABLE_FEAT_VHE := 2 63CTX_INCLUDE_NEVE_REGS := 2 64ENABLE_FEAT_SEL2 := 2 65ENABLE_TRF_FOR_NS := 2 66ENABLE_FEAT_ECV := 2 67ENABLE_FEAT_FGT := 2 68ENABLE_FEAT_TCR2 := 2 69ENABLE_FEAT_S2PIE := 2 70ENABLE_FEAT_S1PIE := 2 71ENABLE_FEAT_S2POE := 2 72ENABLE_FEAT_S1POE := 2 73 74# The FVP platform depends on this macro to build with correct GIC driver. 75$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 76 77# Pass FVP_CLUSTER_COUNT to the build system. 78$(eval $(call add_define,FVP_CLUSTER_COUNT)) 79 80# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 81$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 82 83# Pass FVP_MAX_PE_PER_CPU to the build system. 84$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 85 86# Pass FVP_GICR_REGION_PROTECTION to the build system. 87$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 88 89# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 90$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 91 92# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 93# choose the CCI driver , else the CCN driver 94ifeq ($(FVP_CLUSTER_COUNT), 0) 95$(error "Incorrect cluster count specified for FVP port") 96else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 97FVP_INTERCONNECT_DRIVER := FVP_CCI 98else 99FVP_INTERCONNECT_DRIVER := FVP_CCN 100endif 101 102$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 103 104# Choose the GIC sources depending upon the how the FVP will be invoked 105ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 106 107# The GIC model (GIC-600 or GIC-500) will be detected at runtime 108GICV3_SUPPORT_GIC600 := 1 109GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 110 111# Include GICv3 driver files 112include drivers/arm/gic/v3/gicv3.mk 113 114FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 115 plat/common/plat_gicv3.c \ 116 plat/arm/common/arm_gicv3.c 117 118 ifeq ($(filter 1,${RESET_TO_BL2} \ 119 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 120 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 121 endif 122 123else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 124 125# No GICv4 extension 126GIC_ENABLE_V4_EXTN := 0 127$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 128 129# Include GICv2 driver files 130include drivers/arm/gic/v2/gicv2.mk 131 132FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 133 plat/common/plat_gicv2.c \ 134 plat/arm/common/arm_gicv2.c 135 136FVP_DT_PREFIX := fvp-base-gicv2-psci 137else 138$(error "Incorrect GIC driver chosen on FVP port") 139endif 140 141ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 142FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 143else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 144FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 145 plat/arm/common/arm_ccn.c 146else 147$(error "Incorrect CCN driver chosen on FVP port") 148endif 149 150FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 151 plat/arm/board/fvp/fvp_security.c \ 152 plat/arm/common/arm_tzc400.c 153 154 155PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 156 -Iinclude/lib/psa 157 158 159PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 160 161FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 162 163ifeq (${ARCH}, aarch64) 164 165# select a different set of CPU files, depending on whether we compile for 166# hardware assisted coherency cores or not 167ifeq (${HW_ASSISTED_COHERENCY}, 0) 168# Cores used without DSU 169 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 170 lib/cpus/aarch64/cortex_a53.S \ 171 lib/cpus/aarch64/cortex_a57.S \ 172 lib/cpus/aarch64/cortex_a72.S \ 173 lib/cpus/aarch64/cortex_a73.S 174else 175# Cores used with DSU only 176 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 177 # AArch64-only cores 178 # TODO: add all cores to the appropriate lists 179 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 180 lib/cpus/aarch64/cortex_a65ae.S \ 181 lib/cpus/aarch64/cortex_a76.S \ 182 lib/cpus/aarch64/cortex_a76ae.S \ 183 lib/cpus/aarch64/cortex_a77.S \ 184 lib/cpus/aarch64/cortex_a78.S \ 185 lib/cpus/aarch64/cortex_a78_ae.S \ 186 lib/cpus/aarch64/cortex_a78c.S \ 187 lib/cpus/aarch64/cortex_a710.S \ 188 lib/cpus/aarch64/cortex_a715.S \ 189 lib/cpus/aarch64/cortex_a720.S \ 190 lib/cpus/aarch64/neoverse_n_common.S \ 191 lib/cpus/aarch64/neoverse_n1.S \ 192 lib/cpus/aarch64/neoverse_n2.S \ 193 lib/cpus/aarch64/neoverse_v1.S \ 194 lib/cpus/aarch64/neoverse_e1.S \ 195 lib/cpus/aarch64/cortex_x2.S \ 196 lib/cpus/aarch64/cortex_x4.S 197 endif 198 # AArch64/AArch32 cores 199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 200 lib/cpus/aarch64/cortex_a75.S 201endif 202 203#Build AArch64-only CPUs with no FVP model yet. 204ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 205 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 206 lib/cpus/aarch64/cortex_gelas.S \ 207 lib/cpus/aarch64/nevis.S \ 208 lib/cpus/aarch64/travis.S 209endif 210 211else 212FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 213 lib/cpus/aarch32/cortex_a57.S \ 214 lib/cpus/aarch32/cortex_a53.S 215endif 216 217BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 218 drivers/arm/sp805/sp805.c \ 219 drivers/delay_timer/delay_timer.c \ 220 drivers/io/io_semihosting.c \ 221 lib/semihosting/semihosting.c \ 222 lib/semihosting/${ARCH}/semihosting_call.S \ 223 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 224 plat/arm/board/fvp/fvp_bl1_setup.c \ 225 plat/arm/board/fvp/fvp_cpu_pwr.c \ 226 plat/arm/board/fvp/fvp_err.c \ 227 plat/arm/board/fvp/fvp_io_storage.c \ 228 plat/arm/board/fvp/fvp_topology.c \ 229 ${FVP_CPU_LIBS} \ 230 ${FVP_INTERCONNECT_SOURCES} 231 232ifeq (${USE_SP804_TIMER},1) 233BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 234else 235BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 236endif 237 238 239BL2_SOURCES += drivers/arm/sp805/sp805.c \ 240 drivers/io/io_semihosting.c \ 241 lib/utils/mem_region.c \ 242 lib/semihosting/semihosting.c \ 243 lib/semihosting/${ARCH}/semihosting_call.S \ 244 plat/arm/board/fvp/fvp_bl2_setup.c \ 245 plat/arm/board/fvp/fvp_err.c \ 246 plat/arm/board/fvp/fvp_io_storage.c \ 247 plat/arm/common/arm_nor_psci_mem_protect.c \ 248 ${FVP_SECURITY_SOURCES} 249 250 251ifeq (${COT_DESC_IN_DTB},1) 252BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 253endif 254 255ifeq (${ENABLE_RME},1) 256BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 257 plat/arm/board/fvp/fvp_cpu_pwr.c 258 259BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 260 plat/arm/board/fvp/fvp_realm_attest_key.c 261endif 262 263ifeq (${ENABLE_FEAT_RNG_TRAP},1) 264BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 265endif 266 267ifeq (${RESET_TO_BL2},1) 268BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 269 plat/arm/board/fvp/fvp_cpu_pwr.c \ 270 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 271 ${FVP_CPU_LIBS} \ 272 ${FVP_INTERCONNECT_SOURCES} 273endif 274 275ifeq (${USE_SP804_TIMER},1) 276BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 277endif 278 279BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 280 ${FVP_SECURITY_SOURCES} 281 282ifeq (${USE_SP804_TIMER},1) 283BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 284endif 285 286BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 287 drivers/arm/smmu/smmu_v3.c \ 288 drivers/delay_timer/delay_timer.c \ 289 drivers/cfi/v2m/v2m_flash.c \ 290 lib/utils/mem_region.c \ 291 plat/arm/board/fvp/fvp_bl31_setup.c \ 292 plat/arm/board/fvp/fvp_console.c \ 293 plat/arm/board/fvp/fvp_pm.c \ 294 plat/arm/board/fvp/fvp_topology.c \ 295 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 296 plat/arm/board/fvp/fvp_cpu_pwr.c \ 297 plat/arm/common/arm_nor_psci_mem_protect.c \ 298 ${FVP_CPU_LIBS} \ 299 ${FVP_GIC_SOURCES} \ 300 ${FVP_INTERCONNECT_SOURCES} \ 301 ${FVP_SECURITY_SOURCES} 302 303# Support for fconf in BL31 304# Added separately from the above list for better readability 305ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 306BL31_SOURCES += lib/fconf/fconf.c \ 307 lib/fconf/fconf_dyn_cfg_getter.c \ 308 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 309 310BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 311 312ifeq (${SEC_INT_DESC_IN_FCONF},1) 313BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 314endif 315 316endif 317 318ifeq (${USE_SP804_TIMER},1) 319BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 320else 321BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 322endif 323 324ifeq (${TRANSFER_LIST}, 1) 325include lib/transfer_list/transfer_list.mk 326endif 327 328# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 329ifdef UNIX_MK 330FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 331FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 332 333FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 334$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 335 336ifeq (${TRANSFER_LIST}, 1) 337FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 338 ${PLAT}_tb_fw_config.dts \ 339 ) 340else 341FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 342 ${PLAT}_fw_config.dts \ 343 ${PLAT}_tb_fw_config.dts \ 344 ${PLAT}_soc_fw_config.dts \ 345 ${PLAT}_nt_fw_config.dts \ 346 ) 347 348FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 349FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 350FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 351 352ifeq (${SPD},tspd) 353FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 354FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 355 356# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 357$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 358endif 359 360ifeq (${SPD},spmd) 361 362ifeq ($(ARM_SPMC_MANIFEST_DTS),) 363ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 364endif 365 366FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 367FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 368 369# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 371endif 372 373# Add the FW_CONFIG to FIP and specify the same to certtool 374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 375# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 377# Add the NT_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 379endif 380 381# Add the TB_FW_CONFIG to FIP and specify the same to certtool 382$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 383# Add the HW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 385endif 386 387# Enable dynamic mitigation support by default 388DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 389 390ifneq (${ENABLE_FEAT_AMU},0) 391BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 392 lib/cpus/aarch64/cpuamu_helpers.S 393 394ifeq (${HW_ASSISTED_COHERENCY}, 1) 395BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 396 lib/cpus/aarch64/neoverse_n1_pubsub.c 397endif 398endif 399 400ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 401 ifeq (${ENABLE_FEAT_RAS},1) 402 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 403 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 404 else 405 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 406 endif 407 else 408 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 409 endif 410endif 411 412ifneq (${ENABLE_STACK_PROTECTOR},0) 413PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 414endif 415 416# Enable the dynamic translation tables library. 417ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 418 ifeq (${ARCH},aarch32) 419 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 420 else # AArch64 421 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 422 endif 423endif 424 425ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 426 ifeq (${ARCH},aarch32) 427 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 428 else # AArch64 429 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 430 ifeq (${SPD},tspd) 431 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 432 endif 433 endif 434endif 435 436ifeq (${USE_DEBUGFS},1) 437 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 438endif 439 440# Add support for platform supplied linker script for BL31 build 441$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 442 443ifneq (${RESET_TO_BL2}, 0) 444 override BL1_SOURCES = 445endif 446 447include plat/arm/board/common/board_common.mk 448include plat/arm/common/arm_common.mk 449 450ifeq (${MEASURED_BOOT},1) 451BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 452 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 453 lib/psa/measured_boot.c 454 455BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 456 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 457 lib/psa/measured_boot.c 458endif 459 460ifeq (${DRTM_SUPPORT}, 1) 461BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 462 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 463 plat/arm/board/fvp/fvp_drtm_err.c \ 464 plat/arm/board/fvp/fvp_drtm_measurement.c \ 465 plat/arm/board/fvp/fvp_drtm_stub.c \ 466 plat/arm/common/arm_dyn_cfg.c \ 467 plat/arm/board/fvp/fvp_err.c 468endif 469 470ifeq (${TRUSTED_BOARD_BOOT}, 1) 471BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 472BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 473 474# FVP being a development platform, enable capability to disable Authentication 475# dynamically if TRUSTED_BOARD_BOOT is set. 476DYN_DISABLE_AUTH := 1 477endif 478 479ifeq (${SPMC_AT_EL3}, 1) 480PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 481endif 482 483PSCI_OS_INIT_MODE := 1 484 485ifeq (${SPD},spmd) 486BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 487endif 488 489# Test specific macros, keep them at bottom of this file 490$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 491ifeq (${PLATFORM_TEST_EA_FFH}, 1) 492 ifeq (${FFH_SUPPORT}, 0) 493 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 494 endif 495 496endif 497 498$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 499ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 500 ifeq (${ENABLE_FEAT_RAS}, 0) 501 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 502 endif 503 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 504 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 505 endif 506endif 507 508$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 509ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 510 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 511 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 512 endif 513 ifeq (${ENABLE_SPMD_LP}, 0) 514 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 515 endif 516 ifeq (${ENABLE_FEAT_RAS}, 0) 517 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 518 endif 519 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 520 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 521 endif 522endif 523 524ifeq (${ERRATA_ABI_SUPPORT}, 1) 525include plat/arm/board/fvp/fvp_cpu_errata.mk 526endif 527 528# Build macro necessary for running SPM tests on FVP platform 529$(eval $(call add_define,PLAT_TEST_SPM)) 530